IP Library Granted Patent US 8,338,934
Granted Patent B2
US 8,338,934 · App. 13/049,550 · Granted Dec 25, 2012

Embedded die with protective interposer

Assignee: Marvell World Trade Ltd.
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Quick Facts
Patent No.
US 8,338,934
App. No.
13/049,550
Granted
Dec 25, 2012
Kind
B2
Abstract

Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.

Claims (49)

1. An apparatus comprising:

a substrate having (i) a first laminate layer, (ii) a second laminate layer, (iii) a core material that is disposed between the first laminate layer and the second laminate layer, (iv) a first solder mask layer that is coupled to the first laminate layer, and (v) a second solder mask layer that is coupled to the second laminate layer; and

a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, wherein the interposer has a via formed therein, wherein the via is electrically coupled to the bond pad to further route the electrical signals of the die, and wherein the die and the interposer are embedded in the core material of the substrate.

2. The apparatus of claim 1 , wherein:

the die comprises silicon and the interposer comprises silicon;

the via of the interposer comprises a through-silicon via (TSV);

the dielectric material of the die is a low-k dielectric material;

the bond pad of the die comprises aluminum or copper;

the core material of the substrate comprises a resin; and

the interposer is bonded to the die using a metal-metal bond or a solder bond.

3. The apparatus of claim 1 , wherein:

the die is attached to the first laminate layer using an adhesive to couple an inactive side of the die to the first laminate layer; and

the inactive side of the die is disposed opposite to the active side of the die.

4. The apparatus of claim 1 , further comprising:

one or more routing structures that are electrically coupled to the via of the interposer to further route the electrical signals of the die through the core material, the first laminate layer, and the second laminate layer.

5. The apparatus of claim 4 , wherein the one or more routing structures are electrically coupled to the via of the interposer using a redistribution layer formed on the interposer.

6. The apparatus of claim 4 , wherein the one or more routing structures comprise copper.

7. The apparatus of claim 1 , wherein the substrate further comprises:

a bond pad (i) disposed in the first solder mask layer and (ii) electrically coupled to the via of the interposer to further route the electrical signals of the die.

8. The apparatus of claim 7 , further comprising:

a solder ball coupled to the bond pad that is disposed in the first solder mask layer, the solder ball to further route the electrical signals of the die.

9. The apparatus of claim 8 , wherein the substrate comprises a ball-grid array (BGA) substrate.

10. A method comprising:

forming a substrate comprising (i) a first laminate layer, (ii) a second laminate layer, (iii) a core material that is disposed between the first laminate layer and the second laminate layer of a substrate, (iv) a first solder mask layer that is coupled to the first laminate layer, and (v) a second solder mask layer that is coupled to the second laminate layer; and

attaching a die to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, wherein the interposer has a via formed therein, wherein the via is electrically coupled to the bond pad to further route the electrical signals of the die, and wherein the die and the interposer are embedded in the core material of the substrate.

11. The method of claim 10 , further comprising:

fabricating the die;

fabricating the interposer; and

bonding the interposer to the surface of the active side of the die.

12. The method of claim 10 , wherein:

the die comprises silicon and the interposer comprises silicon;

the via of the interposer comprises a through-silicon via (TSV);

the dielectric material of the die is a low-k dielectric material;

the bond pad of the die comprises aluminum or copper;

the core material of the substrate comprises a resin; and

the interposer is bonded to the die using a metal-metal bond or a solder bond.

13. The method of claim 10 , wherein:

the die is attached to the first laminate layer using an adhesive to couple an inactive side of the die to the first laminate layer; and

the inactive side of the die is disposed opposite to the active side of the die.

14. The method of claim 10 , further comprising:

forming one or more routing structures, to be electrically coupled to the via of the interposer to further route the electrical signals of the die through the core material, the first laminate layer, and the second laminate layer.

15. The method of claim 14 , further comprising:

forming a redistribution layer on the interposer such that the one or more routing structures are electrically coupled to the via of the interposer through the redistribution layer.

16. The method of claim 14 , wherein the one or more routing structures comprise copper.

17. The method of claim 10 , further comprising:

forming a bond pad, wherein the bond pad is (i) disposed in the first solder mask layer, and (ii) electrically coupled to the via of the interposer to further route the electrical signals of the die.

18. The method of claim 17 , further comprising:

attaching a solder ball to the bond pad that is disposed in the first solder mask layer, wherein the solder ball further routes the electrical signals of the die.

19. The method of claim 18 , wherein the solder ball is a part of the substrate comprising a ball-grid array (BGA) substrate.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2011
From: WU, ALBERT; WU, SCOTT
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 025998/0798 →
LICENSE Recorded Mar 22, 2011
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025998/0853 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2011
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025998/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2011
From: MARVELL INTERNATIONAL, LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 025998/0833 →
Continuity (2)
Provisional Application 61315319 · Mar 18, 2010
Related Publication 20110227223A1 · Sep 22, 2011