Non-volatile semiconductor memory device including a variable resistance element

1. A non-volatile semiconductor memory device comprising:

a first line;

a second line intersecting with the first line; and

a memory cell arranged at a position where the second line intersects with the first line;

wherein, the memory cell includes:

a variable resistance element;

a negative resistance element connected in series to the variable resistance element;

a first buffer portion connected to one end of the negative resistance element; and

a second buffer portion connected to the other end of the negative resistance element;

the negative resistance element includes:

a first semiconductor layer constituting the one end; and

a second semiconductor layer constituting the other end;

the first buffer portion includes:

a first buffer layer in contact with the first semiconductor layer; and

a first electrode layer in contact with a surface of the first buffer layer opposite to a surface in contact with the first semiconductor layer; and

the second buffer portion includes:

a second buffer layer in contact with the second semiconductor layer; and

a second electrode layer in contact with a surface of the second buffer layer opposite to a surface in contact with the second semiconductor layer; and wherein

an interatomic distance of the first buffer layer in a direction along a contact surface to the first semiconductor layer is closer to an interatomic distance of the first semiconductor layer in the direction along the contact surface than an interatomic distance of the first electrode layer in the direction along the contact surface; and

an interatomic distance of the second buffer layer in a direction along a contact surface to the second semiconductor layer is closer to an interatomic distance of the second semiconductor layer in the direction along the contact surface than an interatomic distance of the second electrode layer in the direction along the contact surface.

2. The non-volatile semiconductor memory device according to claim 1 , wherein

the memory cell further comprises a rectifier element connected in series to the variable resistance element and the negative resistance element.

3. The non-volatile semiconductor memory device according to claim 2 , wherein:

the rectifier element includes a diode; and

the negative resistance element includes a tunnel diode.

4. The non-volatile semiconductor memory device according to claim 3 , wherein

the diode includes a PIN structure.

5. The non-volatile semiconductor memory device according to claim 2 , wherein

the rectifier element includes a diode, and

the negative resistance element includes a resonance tunnel diode.

6. The non-volatile semiconductor memory device according to claim 5 , wherein

in the resonance tunnel diode a first layer and a second layer are alternately stacked, the first layer being formed of a first material selected from a group composed of SiGe, Si, CaF, CdF, SiO 2 , SiN, Al 2 O 3 , GaAs, AlGaAs, AlAs, InAs, InSb, AlSb, GaSb, and the second layer being formed of a second material selected from the group.

7. The non-volatile semiconductor memory device according to claim 6 , wherein

a band gap of the first material is larger than a band gap of the second material.

8. A non-volatile semiconductor memory device comprising:

a first line;

a second line intersecting with the first line; and

a memory cell arranged at a position where the second line intersects with the first line;

wherein, the memory cell includes:

a variable resistance element;

a negative resistance element connected in series to the variable resistance element;

a first buffer portion connected to one end of the negative resistance element; and

a second buffer portion connected to the other end of the negative resistance element;

the negative resistance element includes:

a first semiconductor layer constituting the one end; and

a second semiconductor layer constituting the other end;

the first buffer portion includes:

a first buffer layer in contact with the first semiconductor layer; and

a first electrode layer in contact with a surface of the first buffer layer opposite to a surface in contact with the first semiconductor layer; and

the second buffer portion includes:

a second buffer layer in contact with the second semiconductor layer; and

a second electrode layer in contact with a surface of the second buffer layer opposite to a surface in contact with the second semiconductor layer; and wherein

the first semiconductor layer and the second semiconductor layer contain dopants, respectively,

the first buffer layer has a thickness sufficient to prevent the dopants contained in the first semiconductor layer from diffusing up to the first electrode layer; and

the second buffer layer has a thickness sufficient to prevent the dopants contained in the second semiconductor layer from diffusing up to the second electrode layer.

9. The non-volatile semiconductor memory device according to claim 8 , wherein

the memory cell further comprises a rectifier element connected in series to the variable resistance element and the negative resistance element.

10. The non-volatile semiconductor memory device according to claim 9 , wherein:

the rectifier element includes a diode; and

the negative resistance element includes a tunnel diode.

11. The non-volatile semiconductor memory device according to claim 10 , wherein

the diode includes a PIN structure.

12. The non-volatile semiconductor memory device according to claim 9 , wherein

the rectifier element includes a diode, and

the negative resistance element includes a resonance tunnel diode.

13. The non-volatile semiconductor memory device according to claim 12 , wherein

in the resonance tunnel diode a first layer and a second layer are alternately stacked, the first layer being formed of a first material selected from a group composed of SiGe, Si, CaF, CdF, SiO 2 , SiN, Al 2 O 3 , GaAs, AlGaAs, AlAs, InAs, InSb, AlSb, GaSb, and the second layer being formed of a second material selected from the group.

14. The non-volatile semiconductor memory device according to claim 13 , wherein

a band gap of the first material is larger than a band gap of the second material.

15. A non-volatile semiconductor memory device comprising:

a first line;

a second line intersecting with the first line; and

a memory cell arranged at a position where the second line intersects with the first line;

wherein, the memory cell includes:

a variable resistance element;

a negative resistance element connected in series to the variable resistance element;

a first buffer portion connected to one end of the negative resistance element; and

a second buffer portion connected to the other end of the negative resistance element;

the negative resistance element includes:

a first semiconductor layer constituting the one end; and

a second semiconductor layer constituting the other end;

the first buffer portion includes:

a first buffer layer in contact with the first semiconductor layer; and

a first electrode layer in contact with a surface of the first buffer layer opposite to a surface in contact with the first semiconductor layer; and

the second buffer portion includes:

a second buffer layer in contact with the second semiconductor layer; and

a second electrode layer in contact with a surface of the second buffer layer opposite to a surface in contact with the second semiconductor layer; and wherein

the first buffer layer has a thickness sufficient to prevent elements of the first electrode layer from diffusing up to the first semiconductor layer; and

the second buffer layer has a thickness sufficient to prevent elements of the second electrode layer from diffusing up to the second semiconductor layer.

16. The non-volatile semiconductor memory device according to claim 15 , wherein

the memory cell further comprises a rectifier element connected in series to the variable resistance element and the negative resistance element.

17. The non-volatile semiconductor memory device according to claim 16 , wherein:

the rectifier element includes a diode; and

the negative resistance element includes a tunnel diode.

18. The non-volatile semiconductor memory device according to claim 17 , wherein

the diode includes a PIN structure.

19. The non-volatile semiconductor memory device according to claim 16 , wherein

the rectifier element includes a diode, and

the negative resistance element includes a resonance tunnel diode.

20. The non-volatile semiconductor memory device according to claim 19 , wherein

in the resonance tunnel diode a first layer and a second layer are alternately stacked, the first layer being formed of a first material selected from a group composed of SiGe, Si, CaF, CdF, SiO 2 , SiN, Al 2 O 3 , GaAs, AlGaAs, AlAs, InAs, InSb, AlSb, GaSb, and the second layer being formed of a second material selected from the group.