Flash memory device, programming method and memory system

1. A programming method for a flash memory device, the programming method comprising:

applying a first pass voltage to a selection word line and a non-selection word line;

applying a local voltage to the non-selection word line;

applying a second pass voltage to the selection word line; and

applying a programming voltage to the selection word line,

wherein the local voltage is lower than the first pass voltage.

2. The programming method of claim 1 , wherein applying the local voltage to the non-selection word line and applying the second pass voltage to the selection word line are performed at the same time.

3. The programming method of claim 1 , wherein a level of the second pass voltage is higher than a level of the first pass voltage.

4. The programming method of claim 1 , wherein applying the first pass voltage to the selection word line and the non-selection word line comprises applying the first pass voltage to a plurality of word lines between first and second selection lines.

5. The programming method of claim 4 , wherein:

the selection word line is disposed between the non-selection word line and the second selection line, and

applying the second pass voltage to the selection word line comprises applying the second pass voltage to a plurality of word lines between the non-selection word line and the second selection line.

6. The programming method of claim 5 , wherein the first pass voltage is applied to word lines between the non-selection word line and the first selection line, when the second pass voltage is applied to the selection word line.

7. The programming method of claim 1 , wherein applying the first pass voltage to the selection word line and the non-selection word line comprises:

applying the first pass voltage to the selection word line, and a plurality of word lines between the selection word line and a first selection line; and

applying a ground voltage to a plurality of word lines between the selection word line and a second selection line.

8. The programming method of claim 7 , wherein the non-selection word line is disposed between the first selection line and the selection word line, and

applying the second pass voltage to the selection word line comprises applying the second pass voltage to a plurality of word lines between the non-selection word line and the second selection line.

9. The programming method of claim 8 , wherein the first pass voltage is applied to word lines between the non-selection word line and the first selection line, when the second pass voltage is applied to the selection word line.

10. The programming method of claim 7 , wherein applying the first pass voltage to the selection word line and the word lines between the selection word line and the first selection line and applying the ground voltage to the word lines between the selection word line and the second selection line are performed at the same time.

11. The programming method of claim 7 , wherein a plurality of memory cells which are connected to a first word line are programmed prior to a plurality of memory cells which are connected to a second word line which is disposed between the first word line and the second selection line.

12. The programming method of claim 1 , wherein applying the first pass voltage to the selection word line and the non-selection word line comprises:

applying the first pass voltage to a plurality of word lines between the selection word line and a first selection line, the selection word line, and a word line group comprising at least one word line which is disposed between the selection word line and a second selection line and is adjacent to the selection word line; and

applying a ground voltage to a plurality of word lines between the word line group and the second selection line.

13. The programming method of claim 12 , wherein the flash memory device stores a plurality of bits per memory cell, and

a plurality of memory cells connected to at least one word line of the word line group pre-store at least one bit per cell.

14. The programming method of claim 12 , wherein:

the non-selection word line is disposed between the first selection line and the selection word line, and

applying the second pass voltage to the selection word line comprises applying the second pass voltage to a plurality of word lines between the non-selection word line and the second selection line.

15. The programming method of claim 12 , wherein a least significant page of a first word line is programmed prior to a least significant page of a second word line which is disposed between the first word line and the second selection line.

16. The programming method of claim 15 , wherein the least significant page of the second word line is programmed prior to a most significant page of the first word line.

17. A flash memory device, comprising:

a memory cell array;

a bias circuit configured to generate voltages applied to the memory cell array during a programming operation; and

a control logic configured to control operation of the bias circuit,

wherein the control logic is further configured to control application of a first pass voltage to a selection word line and non-selection word line of the memory cell array, application of a local voltage to the non-selection word line, application of a second pass voltage to the selection word line, and application of a programming voltage to the selection word line,

wherein the local voltage is lower than the first pass voltage.

18. A memory system, comprising:

a flash memory device, and a controller configured to control the overall operation of the flash memory device,

wherein the flash memory device comprises:

a bias circuit configured to generate voltages applied to the memory cell array during a programming operation; and

a control logic configured to control operation of the bias circuit,

wherein the control logic is further configured to control application of a first pass voltage to a selection word line and non-selection word line of the memory cell array, application of a local voltage to the non-selection word line, application of a second pass voltage to the selection word line, and application of a programming voltage to the selection word line,

wherein the local voltage is lower than the first pass voltage.

19. The memory system of claim 18 , wherein the flash memory device and the controller form a semiconductor disk/drive (SSD).

20. The memory system of claim 18 , wherein the flash memory device and the controller form a memory card.