Push-pull low-noise amplifier with area-efficient implementation
An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric.
1. An amplifier integrated circuit (IC), comprising:
a push-pull configuration including a push stage and a pull stage;
a first loop of wire configured to form a first degeneration inductance of the push stage;
a second loop of wire configured to form a first degeneration inductance of the pull stage, wherein the first loop and the second loop are concentric;
a first trace configured to input a first signal to an amplification stage, wherein the first trace is adjacent and proximate to a first portion of the first loop; and
a second trace configured to input a second signal to the amplification stage,
wherein the second trace is adjacent and proximate to a second portion of the first loop, and
wherein the second portion is arranged across from and opposite to the first portion.
2. The amplifier IC of claim 1 , wherein the first loop, the second loop, the first trace, and the second trace are arranged between the amplification stage and an edge of the amplifier IC.
3. The amplifier IC of claim 1 , wherein:
each of the first loop and the second loop has a shape of a circle, a spiral, or a polygon; and
the first loop has a greater area than the second loop.
4. The amplifier IC of claim 1 , wherein the pull stage includes metal-oxide semiconductor field-effect transistors (MOSFETs) of a first polarity, and wherein the push stage includes MOSFETs of a second polarity that is opposite to the first polarity.
5. A transceiver comprising:
the amplifier IC of claim 1 ,
wherein the transceiver includes a receiver, wherein the receiver includes at least one low-noise amplifier (LNA), and
wherein the at least one LNA includes the amplification stage and the push-pull configuration.
6. A communication device comprising the transceiver of claim 5 .
7. An amplifier integrated circuit (IC), comprising:
a push-pull configuration including a push stage and a pull stage;
a first loop of wire configured to form (i) a first degeneration inductance and (ii) a second degeneration inductance of the push stage; and
a second loop of wire configured to form (i) a first degeneration inductance and (ii) a second degeneration inductance of the pull stage,
wherein the first loop and the second loop are concentric,
wherein the first loop is connected to a common potential, and
wherein the second loop is connected to a supply voltage.
8. An amplifier integrated circuit (IC), comprising:
a push-pull configuration including a push stage and a pull stage;
a first loop of wire configured to form a first degeneration inductance of the push stage; and
a second loop of wire configured to form a first degeneration inductance of the pull stage, wherein the first loop and the second loop are concentric;
wherein each of the first loop and the second loop has a first terminal and a second terminal;
wherein the pull stage comprises a first transistor having (i) a first terminal configured to connect to the first terminal of the first loop, (ii) a second terminal, and (iii) a control terminal;
wherein the push stage comprises a second transistor having (i) a first terminal configured to connect to the first terminal of the second loop, (ii) a second terminal, and (iii) a control terminal; and
wherein the second terminal of the first loop and the second terminal of the second loop are configured to connect to a common potential and a supply voltage, respectively.
9. The amplifier IC of claim 8 , wherein:
the pull stage further comprises a third transistor having (i) a first terminal configured to connect to the second terminal of the first transistor, and (ii) a second terminal; and
the push stage further comprises a fourth transistor having (i) a first terminal configured to connect to the second terminal of the third transistor, and (ii) a second terminal configured to connect to the second terminal of the second transistor.
10. The amplifier IC of claim 9 , further comprising:
an input inductance having (i) a first terminal configured to receive an input signal, and (ii) a second terminal configured to connect to the control terminal of the first transistor; and
a capacitance having (i) a first terminal configured to connect to the control terminal of the first transistor, and (ii) a second terminal configured to connect to the control terminal of the second transistor.
11. An amplifier integrated circuit (IC), comprising:
a push-pull configuration including a push stage and a pull stage;
a first loop of wire configured to form a first degeneration inductance of the push stage; and
a second loop of wire configured to form a first degeneration inductance of the pull stage, wherein the first loop and the second loop are concentric;
wherein each of the first loop and the second loop has a first terminal and a second terminal;
wherein the pull stage comprises:
a first transistor having (i) a first terminal configured to connect to the first terminal of the first loop, (ii) a second terminal, and (iii) a control terminal configured to receive a first input signal; and
a second transistor having (i) a first terminal configured to connect to the second terminal of the first loop, (ii) a second terminal, and (iii) a control terminal configured to receive a second input signal; and
wherein the push stage comprises:
a third transistor having (i) first terminal configured to connect to the first terminal of the second loop, (ii) a second terminal, and (iii) a control terminal; and
a fourth transistor having (i) a first terminal configured to connect to the second terminal of the second loop, (ii) a second terminal, and (iii) a control terminal.
12. The amplifier IC of claim 11 , wherein:
the pull stage further comprises:
a fifth transistor having (i) a first terminal configured to connect to the second terminal of the first transistor, and(ii) a second terminal; and
a sixth transistor having (i) a first terminal configured to connect to the second terminal of the second transistor, and (ii) a second terminal; and
the push stage further comprises:
a seventh transistor having (i) a first terminal configured to connect to the second terminal of the fifth transistor, and (ii) a second terminal configured to connect to the second terminal of the third transistor; and
an eighth transistor having (i) a first terminal configured to connect to the second terminal of the sixth transistor, and (ii) a second terminal configured to connect to the second terminal of the fourth transistor.
13. The amplifier IC of claim 12 , further comprising:
a first capacitance having (i) a first terminal configured to connect to the control terminal of the first transistor, and (ii) a second terminal configured to connect to the control terminal of the third transistor; and
a second capacitance having (i) a first terminal configured to connect to the control terminal of the second transistor, and (ii) a second terminal configured to connect to the control terminal of the fourth transistor.