Logic design modeling and interconnection
A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
1. A reconfigurable interconnect network comprising:
a plurality of simulation processors having a respective plurality of outputs and a respective plurality of inputs, the plurality of simulation processors configured to simulate a circuit model having a plurality of simulation events;
a reconfigurable interconnect stage having a plurality of inputs configured to connect to the plurality of outputs from the simulation processors and further having a plurality of outputs configured to connect to the plurality of inputs of the simulation processors; and
memory, wherein the reconfigurable interconnect network is configured to dynamically re-configure the reconfigurable interconnect stage to a plurality of configurations, each of the plurality of configurations being determined in accordance with respective content stored in the memory, each of the plurality of configurations representing a portion of the circuit model, and each re-configuring to each of the plurality of configurations being in response to one of the plurality of simulation events occurring during simulation of the circuit model, the occurrence of at least one of the simulation events being a simulated asynchronous event determined as a result of simulating the circuit model.
2. The reconfigurable interconnect network of claim 1 ,
wherein the plurality of processor elements are configured to simulate different logic functions according to each of the plurality of simulation events.
3. The reconfigurable interconnect network of claim 1 , wherein the plurality of simulation processors are configured to execute an instruction to perform a simulation of a logic function, the instruction comprising wait data reflecting a time to wait before executing a next instruction.
4. The reconfigurable interconnect network of claim 1 , wherein the plurality of simulation events includes simulated synchronous events and the simulated asynchronous event occurring during simulation of the circuit model on the reconfigurable interconnect network.
5. A method comprising:
configuring a reconfigurable interconnect network to simulate a first logic function in response to a first scheduled event;
executing the first logic function on the reconfigurable interconnect network;
determining if an asynchronous event exists;
if the asynchronous event is determined to exist:
configuring the reconfigurable interconnect network to simulate a third logic function, and
executing the third logic function on the reconfigurable interconnect network; and
if the asynchronous event is determined not to exist:
configuring the reconfigurable interconnect network to simulate a second logic function in response to a second scheduled event, and
executing the second logic function on the reconfigurable interconnect network;
wherein the first logic function, second logic function, and third logic function simulate different partitions of a circuit design model, and wherein the first scheduled event, asynchronous event, and second scheduled event reflect simulated signal states in the circuit design model.
6. The method of claim 5 :
wherein determining if an asynchronous event exist comprises determining if a predefined rule applied to a state of the circuit design model has a positive outcome.
7. The method of claim 5 , wherein the first and second scheduled events include events of multiple different clocks of the circuit design model.
8. The method of claim 5 , wherein outputs of the first logic function, second logic function, and third logic function propagate to a common simulated data path of the circuit design model.
9. A method comprising:
configuring a reconfigurable interconnect network to simulate a first logic partition of a circuit design model;
simulating the first logic partition of the circuit design model on the reconfigurable interconnect network;
configuring the reconfigurable interconnect network to simulate a second logic partition of a circuit design model; and
simulating the second logic partition of the circuit design model on the reconfigurable interconnect network,
wherein the reconfigurable interconnect network comprises a plurality of simulation processors having a respective plurality of outputs and a respective plurality of inputs, and a reconfigurable interconnect stage having a plurality of inputs configured to connect to the plurality of outputs from the simulation processors, the reconfigurable interconnect stage further having a plurality of outputs configured to connect to the plurality of inputs of the simulation processors;
wherein the configuring the reconfigurable interconnect network to simulate the first and the second logic partitions of the circuit design model comprises dynamically re-configuring the reconfigurable interconnect stage to a first configuration and a second configuration respectively; and
wherein the dynamically reconfiguring the reconfigurable interconnect stage to the second configuration is in response to an asynchronous event occurring as an output of the simulation of the first partition of the circuit design model.
10. The method of claim 9 :
wherein simulating the first the second logic partitions of the circuit design model comprises executing a first instruction sequence and a second instruction sequence respectively.
11. The method of claim 9 , wherein dynamically reconfiguring the reconfigurable interconnect stage to the first configuration is in response to a scheduled clock event occurring in a simulation of a third logic partition of the circuit design model.
12. The method of claim 9 , wherein the asynchronous event is included in a sequence of events of the circuit design model, the sequence of events further including simulated synchronous events of the circuit design model.
13. One or more computer readable memory storing computer executable instructions that, when executed, cause a system to perform:
configuring a reconfigurable interconnect network to simulate a first logic function in response to a first scheduled event;
executing the first logic function on the reconfigurable interconnect network;
determining if an asynchronous event exists;
if the asynchronous event is determined to exist:
configuring the reconfigurable interconnect network to simulate a third logic function, and
executing the third logic function on the reconfigurable interconnect network; and
if the asynchronous event is determined not to exist:
configuring the reconfigurable interconnect network to simulate a second logic function in response to a second scheduled event, and
executing the second logic function on the reconfigurable interconnect network;
wherein the first logic function, second logic function, and third Logic function simulate different partitions of a circuit design model, and wherein the first scheduled event, asynchronous event, and second scheduled event reflect simulated signal states in the circuit design model.
14. The computer readable memory of claim 13 :
wherein determining if an asynchronous event exist comprises determining if a predefined rule applied to a state of the circuit design model has a positive outcome.
15. The computer readable memory of claim 13 , wherein the first and second scheduled events include events of multiple different clocks of the circuit design model.
16. The computer readable memory of claim 13 , wherein the first and second scheduled events and the asynchronous event cause changes in states of data paths of the circuit design model.
17. One or more computer readable memory storing computer executable instructions that, when executed, cause a system to perform:
configuring a reconfigurable interconnect network to simulate a first logic partition of a circuit design model;
simulating the first logic partition of the circuit design model on the reconfigurable interconnect network;
configuring the reconfigurable interconnect network to simulate a second logic partition of a circuit design model; and
simulating the second logic partition of the circuit design model on the reconfigurable interconnect network,
wherein the reconfigurable interconnect network comprises a plurality of simulation processors having a respective plurality of outputs and a respective plurality of inputs, and a reconfigurable interconnect stage having a plurality of inputs configured to connect to the plurality of outputs from the simulation processors, the reconfigurable interconnect stage further having a plurality of outputs configured to connect to the plurality of inputs of the simulation processors; and
wherein the configuring the reconfigurable interconnect network to simulate the first and the second logic partitions comprises dynamically re-configuring the reconfigurable interconnect stage to a first configuration and a second configuration respectively, and
wherein the dynamically reconfiguring the reconfigurable interconnect stage to the second configuration is in response to an asynchronous event occurring as an output of the simulation of the first partition of the circuit design model.
18. The computer readable memory of claim 17 : wherein simulating the first the second logic partitions of the circuit design model comprises executing a first instruction sequence and a second instruction sequence respectively.
19. The computer readable memory of claim 17 , wherein dynamically reconfiguring the reconfigurable interconnect stage to the first configuration is in response to a scheduled clock event occurring in a simulation of a third logic partition of the circuit design model.