Structure of power grid for semiconductor devices and method of making the same
View Patent ↗An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.
1. A method comprising:
forming a conductive stud inside a first dielectric layer;
forming one or more conductive paths inside a second dielectric layer, said second dielectric layer being on top of said first dielectric layer, wherein said one or more conductive paths being substantially close to a region of said second dielectric layer remaining on top of a top surface of said conductive stud;
forming a via hole on top of and exposing said top surface of said conductive stud, said via hole exposing at least a portion of sidewalls of said one or more conductive paths;
depositing a conductive liner at a bottom and sidewalls of said via hole; and
depositing a conductive material in said via hole forming a via, said via being in contact with said one or more conductive paths via said conductive liner,
wherein forming said conductive stud comprises forming said conductive stud on top of and being in contact with a contact location of a semiconductor device that is created in a semiconductor substrate with said semiconductor substrate being underneath said first dielectric layer.
2. The method of claim 1 , wherein depositing said conductive material in said via hole comprises selecting said conductive material with a conductivity smaller than conductivity of said conductive liner and depositing said selected conductive material in said via hole.
3. The method of claim 1 , further comprising depositing a third dielectric layer on top of said one or more conductive paths and said second dielectric layer, wherein forming said via hole further comprises forming said via hole in said third dielectric layer and said second dielectric layer.
4. The method of claim 3 , wherein forming said via hole further comprises forming a portion of said via hole in said third dielectric layer, said portion of said via hole in said third dielectric layer being at least as big as, and substantially overlap, said portion of said second dielectric layer remaining on top of said top surface of said conductive stud, such that said portion of said second dielectric layer remaining on top of said top surface of said conductive stud being substantially removed during forming said via hole.
5. The method of claim 1 , wherein said conductive material used in filling said via hole is selected from a group consisting of tungsten (W), aluminum (Al), copper (Cu), and alloy thereof.
6. The method of claim 1 , wherein said region on top of said top surface of said conductive stud has a lateral dimension less than a Blech length of said via made of said conductive material.
7. The method of claim 1 , wherein said via is made of copper (Cu) and has a Blech length of around 10 micrometers.
8. The method of claim 1 , wherein said via is made of conductive material selected from a group consisting of tungsten (W), aluminum (Al), copper (Cu), and alloy thereof.
9. The method of claim 1 , wherein said conductive liner is made of a material being selected from a group consisting of titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), titanium-nitride (TiN), tantalum-nitride (TaN), ruthenium nitride (RuN), and tungsten nitride (WN), and wherein said conductive liner being capable of preventing conductive materials from diffusing therethrough.
10. A method comprising:
providing a first dielectric layer;
forming a conductive stud inside said first dielectric layer;
depositing a second dielectric layer on top of said first dielectric layer;
forming one or more conductive paths inside said second dielectric layer after depositing said second dielectric layer, said one or more conductive paths being adjacent to a region of said second dielectric layer, said region of said second dielectric layer being on top of a top surface of said conductive stud;
removing said region of said second dielectric layer in forming a via hole, said via hole exposing said top surface of said conductive stud and exposing at least a portion of sidewalls of said one or more conductive paths;
depositing a conductive liner at a bottom and sidewalls of said via hole; and
depositing a conductive material in said via hole forming a via, said via being in contact with said one or more conductive paths via said conductive liner.
11. The method of claim 10 , wherein forming said conductive stud comprises forming said conductive stud on top of and being in contact with a contact location of a semiconductor device that is created in a semiconductor substrate with said semiconductor substrate being underneath said first dielectric layer.
12. The method of claim 10 , wherein depositing said conductive material in said via hole comprises selecting said conductive material with a conductivity smaller than conductivity of said conductive liner and depositing said selected conductive material in said via hole.
13. The method of claim 10 , further comprising depositing a third dielectric layer on top of said one or more conductive paths and said second dielectric layer, wherein forming said via hole further comprises forming said via hole in said third dielectric layer and said second dielectric layer.
14. The method of claim 13 , wherein forming said via hole further comprises forming a portion of said via hole in said third dielectric layer, said portion of said via hole in said third dielectric layer being at least as big as, and substantially overlap, said portion of said second dielectric layer remaining on top of said top surface of said conductive stud, such that said portion of said second dielectric layer remaining on top of said top surface of said conductive stud being substantially removed during forming said via hole.
15. The method of claim 10 , wherein said region on top of said top surface of said conductive stud has a lateral dimension less than a Blech length of said via made of said conductive material.
16. The method of claim 10 , wherein said conductive liner is made of a material being selected from a group consisting of titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), titanium-nitride (TiN), tantalum-nitride (TaN), ruthenium nitride (RuN), and tungsten nitride (WN), and wherein said conductive liner being capable of preventing conductive materials from diffusing therethrough.
17. A method comprising:
providing a first dielectric layer;
forming a conductive stud inside said first dielectric layer;
depositing a second dielectric layer on top of said first dielectric layer;
forming at least first and second conductive paths inside said second dielectric layer after depositing said second dielectric layer, said first and second conductive paths being separated by a region of said second dielectric layer, said region of said second dielectric layer being on top of a top surface of said conductive stud;
removing said region of said second dielectric layer in forming a via hole, said via hole exposing said top surface of said conductive stud and exposing at least a portion of sidewalls of both said first and second conductive paths;
depositing a conductive liner at a bottom and sidewalls of said via hole; and
depositing a conductive material in said via hole forming a via, said via being in contact with said first and second conductive paths via said conductive liner.
18. The method of claim 17 , wherein forming said conductive stud comprises forming said conductive stud on top of and being in contact with a contact location of a semiconductor device that is created in a semiconductor substrate with said semiconductor substrate being underneath said first dielectric layer.
19. The method of claim 17 , wherein depositing said conductive material in said via hole comprises selecting said conductive material with a conductivity smaller than conductivity of said conductive liner and depositing said selected conductive material in said via hole.