Low-power analog-circuit architecture for decoding neural signals
A microchip for performing a neural decoding algorithm is provided. The microchip is implemented using ultra-low power electronics. Also, the microchip includes a tunable neural decodable filter implemented using a plurality of amplifiers, a plurality of parameter learning filters, a multiplier, a gain and time-constant biasing circuits; and analog memory. The microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters. The optimization being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input. The microchip, in an operational mode, issues commands to controlling a device using learned mappings.
1. A microchip performing a neural decoding algorithm, said microchip implemented using ultra-low power electronics comprises:
a tunable neural decodable filter implemented using a plurality of amplifiers;
a plurality of parameter learning filters;
a multiplier, wherein linear capacitors at the output of said multiplier integrate output currents to form voltage signals which are used to set bias voltages through gain and time-constant biasing circuits, wherein said bias voltages set the gain and time constant of said tunable neural decodable filter; and
analog memory,
wherein said microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons into motor control parameters, said optimized translation being based on a modified gradient descent least square algorithm wherein update for a given parameter in a filter is proportional to an averaged product of an error in the final output that the filter affects and a filtered version of its input; and said microchip, in operational mode, issues commands to control a device using learned mappings.
2. The microchip of claim 1 , wherein said device comprises a prosthesis or a computer interface.
3. The microchip of claim 1 , wherein said microchip is used in conjunction with a neuromotor prosthetic system.
4. The microchip of claim 1 , wherein said optimized translation is performed according to the following learning rule:
-
(
∇
_
E
i
)
f
,
k
=
-
∫
t
-
σ
t
[
e
i
(
u
)
]
×
(
-
∂
W
f
(
u
)
∂
p
f
,
k
*
N
f
(
u
)
)
ⅆ
u
,
where ∇ E i is a gradient, e i (u) is the error at time u, N ƒ (u) is an N-dimensional vector containing neural signal data at time u, W ƒ (u) is an impulse response kernel corresponding to a filter applied to N ƒ (u), and
∂
W
f
(
u
)
∂
p
f
,
k
is a convolution kernel.
5. The microchip of claim 1 , wherein said microchip is implantable in the brain.
6. A microchip implantable inside a skull, said microchip, in a training mode, learns to perform an optimized translation of a raw neural signal received from a population of cortical neurons in the brain positioned in said skull into motor control parameters, said optimized translation is performed according to the following learning rule:
-
(
∇
_
E
i
)
f
,
k
=
-
∫
t
-
σ
t
2
[
e
i
(
u
)
]
×
(
-
∂
W
f
(
u
)
∂
p
f
,
k
*
N
f
(
u
)
)
ⅆ
u
,
where ∇ E i is a gradient, e i (u) is the error at time u, N ƒ (u) is an N-dimensional vector containing neural signal data at time u, W ƒ (u) is an impulse response kernel corresponding to a filter applied to N ƒ (u), and
∂
W
f
(
u
)
∂
p
f
,
k
is a convolution kernel, said microchip, in an operational mode, issues commands to control a prosthesis using learned mappings.
7. The microchip of claim 6 , wherein said microchip is used in conjunction with a neuromotor prosthetic system.