Mesa heterojunction phototransistor and method for making same
A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.
1. A method of fabricating a two-terminal mesa phototransistor, comprising:
fabricating on a substrate a first semiconductor layer of a first doping type;
fabricating a second semiconductor layer of a second doping type on the first semiconductor layer, the second doping type being opposite to the first doping type, the second semiconductor layer forming portions of a first semiconductor junction with the first semiconductor layer;
etching the first and the second semiconductor layers to produce a mesa structure comprising mesa sidewalls, residue of the first semiconductor layer, the portions of the first semiconductor junction, and residue of the second semiconductor layer;
forming a third doped region within the residue of the second semiconductor layer by introducing a first dopant of the first type into the residue of the second semiconductor layer, thereby creating a second semiconductor junction, wherein the third doped region within the residue of the second semiconductor layer and the second semiconductor junction forms one of an emitter or a collector of the phototransistor;
forming a fourth mesa sidewall doped region by doping a region of the sidewalls with a second dopant of the first type, wherein an electrically active doping level of the fourth mesa sidewall doped region is higher than an electrically active doping level of the second semiconductor layer at the time of formation of the second semiconductor layer, wherein the fourth mesa sidewall doped region is electrically directly connected to the residue of the first semiconductor layer, wherein (i) the fourth mesa sidewall doped region and the residue of the first semiconductor layer and (ii) the residue of the second semiconductor layer form the first semiconductor junction; and
fabricating a dielectric layer on at least a portion of the residue of the second semiconductor layer;
wherein the residue of the first semiconductor layer, the fourth mesa sidewall doped region, the third doped region, and the dielectric layer together completely encapsulate the first semiconductor junction, the residue of the second semiconductor layer without the third doped region, and the second semiconductor junction;
wherein the residue of the first semiconductor layer, the fourth mesa sidewall doped region, the residue of the second semiconductor layer, and the dielectric layer together completely encapsulate the first semiconductor junction;
wherein the first semiconductor junction, the second semiconductor junction, and the dielectric layer together completely encapsulate the residue of the second semiconductor layer without the third doped region; and
wherein the residue of the second semiconductor layer without the third doped region, the third doped region, and the dielectric layer together completely encapsulate the second semiconductor junction.
2. The method of claim 1 , wherein the forming of the third doped region within the residue of the second semiconductor layer and the forming of the fourth mesa sidewall doped region occur simultaneously.
3. The method of claim 1 , wherein the forming of the fourth mesa sidewall doped region comprises doping by at least one of dopant diffusion or ion implantation.
4. The method of claim 1 , wherein final doping type of the fourth mesa sidewall doped region is opposite to doping type of the residue of the second semiconductor layer without the third doped region and beyond the fourth mesa sidewall doped region, and net doping density in the fourth mesa sidewall doped region is at least 3 times as high as net doping density in the residue of the second semiconductor layer without the third doped region and beyond the fourth mesa sidewall doped region.
5. The method of claim 1 , wherein net doping density in the residue of the second semiconductor layer without the third doped region and beyond the fourth mesa sidewall doped region is less than about 10 18 per cubic centimeter.
6. The method of claim 1 , wherein fabricating the second semiconductor layer comprises fabricating at least two sublayers of the second doping type, and wherein the first semiconductor junction and the second semiconductor junction are not both formed with one sublayer.
7. The method of claim 1 , wherein forming the fourth mesa sidewall doped region comprises doping the sidewall to a depth greater than about 100 Angstroms.
8. The method of claim 1 , wherein forming the fourth mesa sidewall doped region comprises doping the sidewall to a depth less than about one tenth of a width of the mesa.
9. The method of claim 1 , wherein forming the fourth mesa sidewall doped region comprises doping the fourth mesa sidewall doped region to a final doping density greater than about 10 17 per cubic centimeter after dopant compensation.
10. The method of claim 1 , wherein fabricating the dielectric layer comprises at least one of growing an oxide, depositing using plasma enhanced chemical vapor deposition, or depositing a high-k dielectric using atomic layer deposition.