Method for forming side contact in semiconductor device through self-aligned damascene process
A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.
1. A method for fabricating a semiconductor device, comprising:
forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, wherein the active regions are extended in one direction and isolated from each other by a line-type trench;
forming an insulation layer on the first sidewall and the second sidewall;
forming an etch stop layer filling a portion of each gap between the active regions;
exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall; and
forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer, wherein the side contact is an opening in the shape of a line, which extends on the first sidewall or the second sidewall of each of the active regions;
wherein the exposing of the insulation layer comprises:
forming a sacrificial layer filling a gap over the etch stop layer;
forming a first recess by performing an etch process onto a portion of the sacrificial layer in such a manner that the etch process stops at the etch stop layer;
forming an etch barrier filling the first recess; and
forming a second recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall by removing the sacrificial layer.
2. The method of claim 1 , wherein the etch process performed onto the portion of the sacrificial layer is a self-aligned etch.
3. The method of claim 1 , wherein the sacrificial layer fills the gap using a spin on coating process.
4. The method of claim 1 , wherein the sacrificial layer includes an oxide layer, and the etch stop layer includes an undoped polysilicon layer.
5. The method of claim 1 , wherein the etch stop layer and the etch barrier include an undoped polysilicon layer.
6. The method of claim 1 , wherein the insulation layer is formed by sequentially forming a liner oxide layer and a liner nitride layer.
7. The method of claim 4 , wherein the forming of the first recess comprises:
performing a dry etch process using a fluorocarbon (HF)-based gas; and
sequentially performing a stripping process and a wet etch process.
8. The method of claim 7 , wherein the dry etch process is performed by adding any one additional gas selected from the group consisting of oxygen (O 2 ), nitrogen (N 2 ), Helium (He), and argon (Ar).
9. The method of claim 4 , wherein the second recess is formed through a wet cleaning process using a HF-based compound.
10. A method for fabricating a semiconductor device, comprising:
forming a plurality of active regions, each having a first sidewall and a second sidewall, by using a hard mask pattern as an etch barrier and etching a semiconductor substrate, wherein the active regions are extended in one direction and isolated from each other by a line-type trench;
forming an insulation layer on the first sidewall and the second sidewall;
forming an etch stop layer filling a portion of each gap between the active regions;
forming a sacrificial layer filling a gap over the etch stop layer;
forming a sacrificial pattern providing a first recess by etching a portion of the sacrificial layer;
forming an etch barrier filling the first recess;
exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall by removing the sacrificial pattern; and
forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer, wherein the side contact is an opening in the shape of a line, which extends on the first sidewall or the second sidewall of each of the active regions.
11. The method of claim 10 , wherein the sacrificial pattern providing the first recess is formed using a self-aligned etch between the hard mask pattern and the sacrificial layer.
12. The method of claim 10 , wherein the etch stop layer and the etch barrier include an undoped polysilicon layer.
13. The method of claim 10 , wherein the insulation layer is formed by sequentially forming a liner oxide layer and a liner nitride layer.
14. The method of claim 11 , wherein the sacrificial layer includes an oxide layer, and the hard mask pattern includes a nitride layer.
15. The method of claim 14 , wherein the oxide layer is formed through a spin on coating process.
16. The method of claim 14 , wherein the forming of the sacrificial pattern providing the first recess comprises:
performing a dry etch process using a fluorocarbon (HF)-based gas; and
sequentially performing a stripping process and a wet etch process.
17. The method of claim 14 , wherein the second recess is formed through a wet cleaning process using a HF-based compound.
18. The method of claim 16 , wherein the dry etch process is performed by adding any one additional gas selected from the group consisting of oxygen (O 2 ), nitrogen (N 2 ), Helium (He), and argon (Ar).