Semiconductor device having multiple storage regions
View Patent ↗One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films.
1. A semiconductor device comprising:
a groove that is formed in a semiconductor substrate;
bottom oxide films that are formed on both side faces of the groove;
two charge storage layers that are formed on side faces of the bottom oxide films;
top oxide films that are formed on side faces of the two charge storage layers, wherein said top oxide films physically contact said bottom oxide films in the groove;
a silicon oxide layer that is formed on a bottom face of the groove, and has a smaller film thickness than one of the top oxide films, wherein said silicon oxide layer has a smaller film thickness than a film thickness of one of the bottom oxide films located below said two charge storage layers; and
a word line that is formed on side faces of the top oxide films and on the silicon oxide layer, wherein said word line extends below said two charge storage layers.
2. The semiconductor device of claim 1 , wherein said word line is a gate electrode corresponding to the two charge storage layers.
3. The semiconductor device of claim 1 , further comprising
a bit line that is provided on either side of the groove and in the semiconductor substrate.
4. The semiconductor device of claim 1 , wherein the charge storage layers include silicon nitride films.
5. The semiconductor device of claim 1 , wherein the charge storage layers include floating gates.
6. A computing device comprising:
a processor;
an input component coupled to the processor;
an output component coupled to the processor; and
a memory coupled to the processor, the memory comprising:
a groove that is formed in a semiconductor substrate;
bottom oxide films that are formed on both side faces of the groove;
two charge storage layers that are formed on side faces of the bottom oxide films;
top oxide films that are formed on side faces of the two charge storage layers, wherein said top oxide films physically contact said bottom oxide films in the groove;
a silicon oxide layer that is formed on a bottom face of the groove, and has a smaller film thickness than one of the top oxide films, wherein said silicon oxide layer has a smaller film thickness than a film thickness of one of the bottom oxide films located below said two charge storage layers; and
a word line that is formed on side faces of the top oxide films and on the silicon oxide layer, wherein said word line extends below said two charge storage layers.
7. The computing device of claim 6 , further comprising:
a codec coupled to the processor.
8. The computing device of claim 6 , wherein said computing device is a personal digital assistant.
9. The computing device of claim 6 , wherein said computing device is a gaming system.
10. The computing device of claim 6 , wherein said computing device is portable notebook computer.
11. The computing device of claim 6 , wherein said memory is flash memory.
12. The computing device of claim 6 , wherein said memory is NAND flash memory.
13. The computing device of claim 6 , wherein said memory is NOR flash memory.
14. A semiconductor device comprising:
a groove that is formed in a semiconductor substrate;
bottom oxide films that are formed on both side faces of the groove;
two charge storage layers that are formed on side faces of the bottom oxide films;
top oxide films that are formed on side faces of the two charge storage layers;
a silicon oxide layer that is formed on a bottom face of the groove, and has a smaller film thickness than one of the top oxide films, wherein said silicon oxide layer has a smaller film thickness than a film thickness of one of the bottom oxide films located below said two charge storage layers, wherein said silicon oxide layer directly contacts said top oxide films and said bottom oxide films in the groove; and
a word line that is formed on side faces of the top oxide films and on the silicon oxide layer, wherein said word line extends below said two charge storage layers.
15. The semiconductor device of claim 14 , wherein said word line is a gate electrode corresponding to the two charge storage layers.
16. The semiconductor device of claim 14 , further comprising
a bit line that is provided on either side of the groove and in the semiconductor substrate.
17. The semiconductor device of claim 14 , wherein the charge storage layers include silicon nitride films.
18. The semiconductor device of claim 14 , wherein the charge storage layers include floating gates.
19. The semiconductor device of claim 14 , wherein said silicon oxide layer has a smaller film thickness than said top oxide films.
20. The semiconductor device of claim 14 , wherein said silicon oxide layer has a smaller film thickness than said bottom oxide films.