Flash memory device having dummy cell
A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.
1. A method of erasing a flash memory device, the method comprising:
erasing memory cells connected to a plurality of word lines; and
programming a memory cell connected to a dummy word line to a predetermined state.
2. The method as set forth in claim 1 , wherein the predetermined state is a highest state among a plurality of program states of the memory cell.
3. The method as set forth in claim 1 , wherein a threshold voltage of the memory cell corresponding to the predetermined state is lower than a pass voltage supplied to an unselected word line during a program operation.
4. The method as set forth in claim 1 , wherein the memory cell connected to the dummy word line is programmed in an incremental step pulse programming (ISPP) mode.
5. The method as set forth in claim 1 , wherein the memory cell connected to the dummy word line is programmed in a single pulse programming mode or multiple pulse programming mode.
6. The method as set forth in claim 1 , further comprising:
determining a position of the dummy word line among the plurality of word lines to minimize a charge sharing in a string including a program-inhibited memory cell.
7. The method as set forth in claim 6 , further comprising:
storing the determined position as position information in a storage device.
8. The method as set forth in claim 7 , further comprising:
receiving the position of the dummy word line from the storage device before programming the memory cell connected to the dummy word line.
9. The method as set forth in claim 1 , further comprising:
supplying a same voltage to the memory cell connected to the dummy word line as that supplied to a control gate of unselected memory cells during programming, reading, or erasing operations.