IP Library Granted Patent US 8,359,409
Granted Patent B2
US 8,359,409 · App. 13/543,954 · Granted Jan 22, 2013

Aligning protocol data units

Inventors: Kartik Raju (Sunnyvale, CA); Mehmet Un (Santa Clara, CA)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,359,409
App. No.
13/543,954
Granted
Jan 22, 2013
Kind
B2
Abstract

An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Claims (29)

1. A method for writing one or more protocol data units to a word aligned queue comprising:

receiving, at a media access control physical-layer coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor, a first protocol data unit (PDU) from system memory, the system memory being byte aligned;

preparing, by the MPC, the first PDU for storage in a transmission physical-layer (PHY) queue, the first PDU being byte aligned, the transmission PHY queue being word aligned and comprising a plurality of word lines; and

writing, by the MPC, the first PDU to the transmission PHY queue.

2. The method of claim 1 , further comprising:

receiving, at the MPC from the transmission PHY queue, a selected word line comprising an end portion of a second PDU, the second PDU being previously stored in the transmission PHY queue;

determining, by the MPC, a number of bytes unwritten to the selected word line;

appending, by the MPC, a beginning portion of the first PDU to the end portion of the second PDU to create a new word, wherein the beginning portion of the first PDU is equal in size to the number of bytes unwritten to the selected word line; and

writing, by the MPC, the new word to the selected word line of the transmission PHY queue.

3. The method of claim 2 , further comprising storing the selected word line in a register in the MPC.

4. The method of claim 1 , wherein the transmission PHY queue is a first-in-first-out (FIFO) queue.

5. The method of claim 1 , wherein the first PDU is a MAC PDU (MPDU).

6. The method of claim 1 , wherein the first PDU has been processed by the MPC based on a TX descriptor from the MAC processor.

7. The method of claim 1 , further comprising using a pointer to store a memory location of where the first PDU ends.

8. An apparatus for writing one or more protocol data units to a word aligned queue comprising:

a media access control physical-layer coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor configured to:

receive a first protocol data unit (PDU) from system memory, the system memory being byte aligned;

prepare the first PDU for storage in a transmission physical-layer (PHY) queue, the first PDU being byte aligned, the transmission PHY queue being word aligned and comprising a plurality of word lines; and

write the first PDU to the transmission PHY queue.

9. The apparatus of claim 8 , wherein the MPC is further configured to:

receive a selected word line comprising an end portion of a second PDU, the second PDU being previously stored in the transmission PHY queue;

determine a number of bytes unwritten to the selected word line;

append a beginning portion of the first PDU to the end portion of the second PDU to create a new word, wherein the beginning portion of the first PDU is equal in size to the number of bytes unwritten to the selected word line; and

write the new word to the selected word line of the transmission PHY queue.

10. The apparatus of claim 9 , wherein the MPC is further configured to store the selected word line in a register in the MPC.

11. The apparatus of claim 8 , wherein the transmission PHY queue is a first-in-first-out (FIFO) queue.

12. The apparatus of claim 8 , wherein the first PDU is a MAC PDU (MPDU).

13. The apparatus of claim 8 , wherein the first PDU has been processed by the MPC based on a TX descriptor from the MAC processor.

14. The apparatus of claim 8 , wherein the MPC is further configured to store a memory location of where the first PDU ends.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2012
From: RAJU, KARTIK; UN, MEHMET
To: FUJITSU LIMITED
Reel/Frame 028510/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2012
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 028510/0358 →
CHANGE OF NAME Recorded Jul 9, 2012
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028510/0863 →
Continuity (2)
Division 12127616 · May 27, 2008
Related Publication 20120275471A1 · Nov 1, 2012