Memory element with small threshold voltage variance and high-speed logic element with low power consumption
A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.
1. A semiconductor device comprising:
a semiconductor layer;
an element isolation region formed in the semiconductor layer for separation of the semiconductor layer into a memory element part and a logic element part;
a first field-effect transistor formed in the memory element part of the semiconductor layer and having a first gate electrode on a first surface side of the semiconductor layer;
a second field-effect transistor formed in the memory element part of the semiconductor layer and having a second gate electrode on a second surface side opposite to the first surface and a source and drain region in common with a source and drain region of the first field-effect transistor;
a third field-effect transistor formed in the logic element part of the semiconductor layer and having a third gate electrode on the second surface side;
a first insulating film formed on the semiconductor layer to cover the first field-effect transistor; and
a second insulating film formed on the semiconductor layer to cover the second field-effect transistor and the third field-effect transistor,
wherein the first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors, and
the first gate electrode and the second gate electrode are electrically connected;
wherein the first gate electrode and the second gate electrode are electrically connected by a contact portion formed through the element isolation region.
2. The semiconductor device according to claim 1 , wherein the first field-effect transistor has
the first gate electrode formed on the first surface of the semiconductor layer via a first gate insulating film, and
a first source and drain region formed in the semiconductor layer at both sides of the first gate electrode,
the second field-effect transistor has
the second gate electrode formed on the second surface of the semiconductor layer via a second gate insulating film, and
a second source and drain region formed in the semiconductor layer at both sides of the second gate electrode,
the third field-effect transistor has
the third gate electrode formed on the second surface of the semiconductor layer via a third gate insulating film, and
a third source and drain region formed in the semiconductor layer at both sides of the third gate electrode,
the first gate electrode and the second gate electrode are formed in opposed locations, and
the first source and drain region and the second source and drain region are formed by a common source and drain region.
3. The semiconductor device according to claim 2 , wherein a memory element is connected to the first source and drain region.
4. The semiconductor device according to claim 1 , wherein the memory element part includes plural field-effect transistors, and part of the transistors are the first field-effect transistor and the second field-effect transistor.
5. The semiconductor device according to claim 1 , wherein the third field-effect transistor is a partially-depleted field-effect transistor.
6. The semiconductor device according to claim 1 , wherein one of the first gate electrode and the second gate electrode is provided at the inner side of the other in a planar layout.