Switched-capacitor pipeline ADC stage
A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.
1. A switched-capacitor pipeline ADC stage comprising
an input stage comprising a quantizing ADC and a DAC,
a sampling capacitor having an input electrode which is switchably connectable to each of an input to the ADC stage and an output of the DAC, and
an output stage, connected to an output electrode of the sampling capacitor and for determining the difference between a signal at the DAC output and a signal at the ADC input,
characterized in that
the ADC stage further comprises a reset switch connected to the sampling capacitor and being for resetting the charge in the sampling capacitor, and is arranged to be closed, in use, for a predetermined period immediately prior to a connecting of the input electrode to the input to the quantizing ADC.
2. An ADC stage according to claim 1 , wherein the output stage comprises transfer capacitance means connected between a first input of an operational amplifier and an output of the operational amplifier.
3. An ADC stage according to claim 2 , wherein the transfer capacitance means is arranged to be discharged when the input electrode is connected to the input to the quantizing ADC.
4. An ADC stage according to claim 2 , wherein the transfer capacitance means is arranged to be discharged when the reset switch is closed.
5. An ADC stage according to claim 1 comprising a MDAC stage wherein the sampling capacitor comprises a part of the transfer capacitance means, and the sampling capacitor comprises a plurality of individual capacitors having a common output electrode and each having an individual input electrode which input electrodes together comprise the input electrode, the individual input electrodes being individually switchably connectable to either one of two reference voltages, and being switchably connectable to the input to the ADC stage, and wherein the reset switch is arranged to be closed, in use, for the predetermined period immediately prior to the connecting of the individual input electrodes to the input to the quantizing ADC.
6. An ADC stage according to claim 5 , wherein the two reference voltages are equal in magnitude and opposite in sign.
7. A switched-capacitor pipeline ADC stage comprising
an input stage comprising a quantizing ADC having differential inputs and a DAC having differential outputs,
first and second sampling capacitors each having a respective input electrode which is switchably connectable to a respective differential input to the ADC stage and the respective differential output of the DAC, and
an output stage, comprising a differential amplifier having differential inputs connected respectively to an output electrode of each of the first and second sampling capacitors,
characterized in that
the ADC stage further comprises a reset switch connected between the respective first and second sampling capacitors and being for balancing the charge between the sampling capacitors, and being arranged to be closed, in use, for a predetermined period immediately prior to connecting of the input electrodes to the respective differential input to the quantizing ADC.
8. An ADC stage according to claim 7 , wherein the output stage comprises a first transfer capacitance means connected between a first input of an operational amplifier and an inverting output of the operational amplifier, and a second transfer capacitance means connected between a second input of the operational amplifier and a non-inverting output of the operational amplifier.
9. An ADC stage according to claim 8 , wherein the transfer capacitance means are arranged such that respective charges on them are either discharged or made to balance when the input electrodes are connected to the respective differential input to the quantizing ADC.
10. An ADC stage according to claim 8 , wherein the transfer capacitance means are arranged such that respective charges on them are either discharged or made to balance when the reset switch is closed.
11. An ADC stage according to claim 8 , wherein the reset switch is arranged such that the respective input electrodes of the first and second sampling capacitors are connected to ground when the reset switch is closed.
12. An ADC stage according to claim 8 comprising an MDAC stage wherein the sampling capacitors comprise a part of the transfer capacitance means, and the each sampling capacitor comprises a plurality of individual capacitors having a common output electrode and each having an individual input electrode which input electrodes together comprise the respective sampling capacitor's input electrode, the individual input electrodes being individually switchably connectable to a reference voltage, and being switchably connectable to the respective input to the ADC stage and wherein the reset switch is arranged to be closed, in use, for the predetermined period immediately prior to the connecting of the individual input electrodes to the respective differential input to the quantizing ADC stage.
13. An ADC stage according to claim 7 wherein the differential outputs of the DAC have respective voltages which are equal in magnitude and opposite in sign.