IP Library Granted Patent US 8,363,047
Granted Patent B2
US 8,363,047 · App. 13/437,237 · Granted Jan 29, 2013

Active matrix display device

Inventors: Toshio Miyazawa (Chiba, JP); Iwao Takemoto (Mobara, JP); Atsushi Hasegawa (Togane, JP); Masashiro Maki (Mobara, JP); Kazutaka Goto (Mobara, JP)
Assignees: Hitachi Displays, Ltd.; Panasonic Liquid Crystal Display Co., Ltd.
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Quick Facts
Patent No.
US 8,363,047
App. No.
13/437,237
Granted
Jan 29, 2013
Kind
B2
Abstract

A display device includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Claims (51)

1. A display device comprising:

a display panel;

a display driving circuit including a shift register formed on the display panel,

the shift register including a connection of a plurality of stages,

a first stage thereof including a first transistor and a second transistor,

a second stage thereof including a third transistor and a fourth transistor,

the first transistor including a control electrode, an input electrode and an output electrode, and

the third transistor including a control electrode, an input electrode and an output electrode;

a first synchronous pulse input line connected to the input electrode of the first transistor;

a second synchronous pulse input line connected to the input electrode of the third transistor; and

wherein a voltage of the control electrode of the first transistor is boosted by a voltage of the first synchronous pulse changing from a low level to a high level,

the second transistor connects the control electrode of the first transistor and a constant voltage line when the second transistor is in an on state,

a voltage of the control electrode of the third transistor is boosted by a voltage of the second synchronous pulse changing from a low level to a high level,

the fourth transistor connects the control electrode of the third transistor and a constant voltage line when the fourth transistor is in an on state, and

the first stage outputs a signal for switching the fourth transistor to an off state.

2. A display device according to claim 1 ,

wherein the first transistor outputs a scanning signal to the display panel and the fourth transistor outputs a scanning signal to the display panel.

3. A display device comprising:

a display panel including a plurality of pixel regions;

a display driving circuit including a shift register formed on the display panel and outputting a scanning signal to the pixel region,

the shift register including a connection of a plurality of stages,

a first stage thereof including a first transistor and a second transistor,

a second stage thereof including a third transistor and a fourth transistor,

the first transistor including a control electrode, an input electrode and an output electrode, and

the third transistor including a control electrode, an input electrode and an output electrode;

a first synchronous pulse input line connected to the input electrode of the first transistor;

a second synchronous pulse input line connected to the input electrode of the third transistor; and

wherein a voltage of the control electrode of the first transistor is boosted by a voltage of the first synchronous pulse changing from a low level to a high level,

the second transistor connects the control electrode of the first transistor and a constant voltage line when the second transistor is in an on state,

a voltage of the control electrode of the third transistor is boosted by a voltage of the second synchronous pulse changing from a low level to a high level,

the fourth transistor connects the control electrode of the third transistor and a constant voltage line when the fourth transistor is in an on state, and

the first stage outputs a signal for switching the fourth transistor to an off state.

4. A display device according to claim 3 ,

wherein the first transistor outputs an output signal for the scanning signal to the pixel region and the fourth transistor outputs an output signal for the scanning signal to the pixel region.

5. A display device comprising:

a display panel including a plurality of pixel regions;

a display driving circuit including a ratioless dynamic shift register formed on the display panel and outputting a scanning signal to the pixel region,

the ratioless dynamic shift register including a connection of a plurality of stages,

a first stage thereof including a first transistor and a second transistor,

a second stage thereof including a third transistor and a fourth transistor,

the first transistor including a control electrode, an input electrode and an output electrode, and

the third transistor including a control electrode, an input electrode and an output electrode;

a first synchronous pulse input line connected to the input electrode of the first transistor;

a second synchronous pulse input line connected to the input electrode of the third transistor; and

wherein a voltage of the control electrode of the first transistor is boosted by a voltage of the first synchronous pulse changing from a low level to a high level,

the second transistor connects the control electrode of the first transistor and a constant voltage line when the second transistor is in an on state,

a voltage of the control electrode of the third transistor is boosted by a voltage of the second synchronous pulse changing from a low level to a high level,

the fourth transistor connects the control electrode of the third transistor and a constant voltage line when the fourth transistor is in an on state, and

the first stage outputs a signal for switching the fourth transistor to an off state.

6. A display device according to claim 5 ,

wherein the first transistor outputs an output signal for the scanning signal to the pixel region and the fourth transistor outputs an output signal for the scanning signal to the pixel region.

Priority Claims (2)
JP 2000-320745 · Oct 20, 2000 · national
JP 2001-296176 · Sep 27, 2001 · national
Continuity (5)
Continuation 12127242 · May 27, 2008
Continuation 11797033 · Apr 30, 2007
Continuation 10857944 · Jun 2, 2004
Continuation 09981804 · Oct 19, 2001
Related Publication 20120188219A1 · Jul 26, 2012