Semiconductor structure and method for manufacturing the same
The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.
1. A semiconductor structure, comprising
an SOI substrate comprising an SOI layer, a first buried insulating layer, an additional SOI layer, a second buried insulating layer and a base substrate from top to bottom;
a shallow trench isolation structure embedded in the SOI substrate and located above the second buried insulation layer to provide an active region;
a gate formed in the active region;
source/drain regions on both sides of the gate;
a back-gate region forming by reducing resistance of the additional SOI layer; and
a contact,
characterized in that
the back-gate region comprises at least a portion of the additional SOI layer below the source or drain region and below the gate; and
the portion of the contact outside the source or drain region extends to the back-gate region to provide a common electrical contact between the source or drain region and the back-gate region.
2. The semiconductor structure according to claim 1 , characterized in that the portion of the additional SOI layer below the source or drain region is formed as an isolating dielectric filling region adjacent to the back-gate region.
3. The semiconductor structure according to claim 1 , characterized in that the portion of the contact outside the source or drain region is formed in the shallow trench isolation structure and contacts one side surface of the back-gate region.
4. The semiconductor structure according to claim 1 , characterized in that it further comprises raised source/drain regions on the source/drain regions.
5. The semiconductor structure according to claim 1 , characterized in that the first buried insulating layer and the second buried insulating layer are buried oxide layers.
6. A method for manufacturing a semiconductor structure, comprising:
providing an SOI substrate which comprises an SOI layer, a first buried insulating layer, an additional SOI layer, a second buried insulating layer and a base substrate from top to bottom;
forming a shallow trench isolation structure embedded in the SOI substrate and located above the second buried insulation layer to provide an active region;
forming a back-gate region by reducing resistance of the additional SOI layer;
forming a gate and source/drain regions on both sides of the gate on the SOI substrate in the active region;
the back-gate region comprising at least a portion of the additional SOI layer below the source or drain region and below the gate; and
forming a contact having a portion outside a source or drain region which extends to the back-gate region to provide a common electrical contact between the source or drain region and the back-gate region.
7. The method according to claim 6 , characterized in that the step of forming a back-gate region by reducing resistance of the additional SOI layer comprises performing n-type or p-type doping with a doping concentration of about 10 18 -10 21 cm −3 .
8. The method according to claim 6 , characterized in that an isolating dielectric filling region is formed in the region of the additional SOI layer below the source or drain region and adjacent to the back-gate region.
9. The method according to claim 8 , characterized in that the step of forming an isolating dielectric filling region comprises:
performing n-type heavily doping to a portion of the additional SOI layer before formation of the shallow trench isolation structure;
forming an isolation trench to expose one side of the n-type heavily doped region;
removing the n-type heavily doped region; and
filling with an isolating dielectric.
10. The method according to claim 9 , characterized in that the step of performing n-type heavy doping comprises performing ion implantation with As or P.
11. The method according to claim 9 , characterized in that the doping concentration is larger than 10 18 cm −3 .
12. The method according to claim 6 , characterized in that the portion of the contact outside the source or drain region extends into the shallow trench isolation structure and contacts one side surface of the back-gate region.
13. The method according to claim 12 , characterized in that the step of forming the contact with one side surface of the back-gate region comprises:
forming a contact hole which has a portion extending into the shallow trench isolation structure to expose one side surface of the back-gate region;
filling the contact hole with a conductive material; and
performing a planarization process.
14. The method according to claim 13 , characterized in that the conductive material is one selected from a group consisting of W, Al, Cu, TiAl, and combinations thereof.
15. The method according to claim 14 , characterized in that a liner is formed before filling with the conductive material.
16. The method according to claim 15 , characterized in that the material of the liner is one selected from a group consisting of Ta, TaN, Ti, TiN, Ru, and combinations thereof.
17. The method according to claim 16 , characterized in that raised source/drain regions are formed on the source/drain regions.
18. The method according to claim 6 , characterized in that the first buried insulating layer and the second buried insulating layer are buried oxide layers.