Memory device for reducing programming time

1. A memory device comprising:

first and second planes each comprising a plurality of non-volatile memory cells;

first and second page buffers corresponding to the first and second planes, respectively;

an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers;

a flash interface connected to the input/output control unit; and

a host connected to the flash interface, wherein the input/output control unit allows the data stored in the first and second page buffers to be transmitted between each other when the control signal is activated.

2. The memory device according to claim 1 , wherein the input/output control unit selectively provides a path of data transmission between the first and second buffers or a path of data transmission between the flash interface and the first and second page buffers, in response to the control signal.

3. The memory device according to claim 2 , wherein the control signal is a test mode signal which is activated when the data transmission between the first and second planes is allowed in a state in which the host is excluded.

4. The memory device according to claim 2 , wherein the input/output control unit provides the path of the data transmission between the flash interface and the first and second page buffers when the control signal is deactivated.

5. The memory device according to claim 1 , further comprising: a first global line group connected to the first page buffer; and a second global line group connected to the second page buffer.

6. The memory device according to claim 4 , wherein the flash interface and the host are connected to each other through data lines, and the number of data lines is smaller than the number of global lines of the first and second global line groups.