Generation and detection of non-binary digital sequences
Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.
1. A method for determining with a processor of a correlation value between a first sequence of n-state symbols and a second sequence of n-state symbols, an n-state symbol having one of n states with n an integer and n>2, the n-state symbol being represented by a signal, comprising:
providing the processor with the first sequence of n-state symbols, wherein the first sequence has at least three n-state symbols each with a different one of the n states;
adding by the processor of a first value to a sum whenever an n-state symbol in the first sequence is identical to a corresponding symbol in the second sequence which has at least three n-state symbols each with a different one of the n states; and
generating by the processor of a signal representing the correlation value when all signals representing the n-state symbols of the first sequence have been processed to determine the sum.
2. The method as claimed in claim 1 , further comprising subtracting by the processor of a second value from the sum whenever an n-state symbol in the first sequence is different from a corresponding symbol in the second sequence.
3. The method as claimed in claim 1 , wherein the method is applied to determine if the first sequence is a maximum length sequence determined by a correlation graph with a single peak.
4. The method as claimed in claim 3 , further comprising combining each n-state symbol of the first sequence with a corresponding symbol of a third sequence by applying an implementation of an n-state logic function to generate a fourth sequence of n-state symbols.
5. The method as claimed in claim 1 , wherein the first sequence is is applied in a data storage system.
6. The method as claimed in claim 1 , wherein the first sequence is applied in a digital document.
7. The method as claimed in claim 1 , wherein the first sequence is applied in a communication device.
8. The method as claimed in claim 1 , wherein the n-state symbol is represented by a plurality of binary signals.
9. A method for determining with a processor a plurality of correlation values between a first sequence of n-state symbols wherein the first sequence has at least three n-state symbols each with a different state of the n states and a second sequence of symbols, an n-state symbol having one of n states with n being an integer with n>2, the n-state symbol being represented by a signal, comprising:
determining a plurality of sequences from the second sequence;
determining by the processor of a correlation value between the first sequence and the second sequence by adding by the processor a first value to a sum for each n-state symbol in the first sequence that is identical to a corresponding symbol in the second sequence, the correlation value being part of the plurality of correlation values; and
determining by the processor of other correlation values of the plurality of correlation values by correlating the first sequence with each of the plurality of sequences;
determining by the processor from the plurality of correlation values that the first sequence is a maximum length sequence determined by a correlation graph with a single peak.
10. The method as claimed in claim 9 , wherein the first sequence of n-state symbols is determined by a Linear Feedback Shift Register (LFSR).
11. The method as claimed in claim 9 , further comprising:
combining each n-state symbol of the first sequence with a corresponding symbol of a third sequence by applying an implementation of an n-state logic function to generate a fourth sequence of n-state symbols.
12. The method as claimed in claim 9 , wherein the first sequence is applied in a communication device.
13. The method as claimed in claim 9 , wherein the n-state symbol is represented by a plurality of binary symbols.
14. An apparatus for providing a plurality of signals representing a plurality of correlation values between a first sequence of at least 3 n-state symbols each having a different of the n-states and a second sequence of n-state symbols, each n-state symbol having one of n states with n being an integer with n>2 and being represented by a signal, comprising:
a processor enabled to execute instructions to perform the steps:
comparing an n-state symbol in the first sequence with a corresponding n-state symbol in the second sequence;
adding a first value to a sum whenever the n-state symbol in the first sequence is identical to the corresponding n-state symbol of the second sequence; and
determining a correlation value from the sum after the n-state symbols in the first sequence and the corresponding n-state symbols in the second sequence have been compared.
15. The apparatus of claim 14 , wherein the n-state symbol is represented by a plurality of binary signals.
16. The apparatus of claim 14 , wherein the apparatus is part of a communication system.
17. The apparatus of claim 14 , wherein the apparatus is part of a data storage system.
18. The apparatus of claim 15 , wherein the apparatus is part of a communication system.
19. The apparatus of claim 14 , wherein the n-state symbol is represented by a non-magnitude dependent signal.
20. The apparatus of claim 14 , wherein the first sequence of n-state symbols is applied to generate a third sequence of symbols.