Clock recovery circuit and data recovery circuit

1. A clock recovery circuit for recovering clock signal based on inputted serial signal, comprising:

a plurality of samplers configured to sample a serial input signal in synchronization with a plurality of first clock signals having different phases respectively and to output a plurality of sampling data pieces;

a phase comparison circuit configured to output a serial phase information signal on the basis of the sampling data pieces, the serial phase information signal representing a phase relationship between a clock of the serial input signal and the different phases of the first clock signals;

a serial-parallel conversion circuit configured to perform a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a frequency lower than that of the first clock signals, and to output a parallel phase information signal;

a digital filtering circuit configured to calculate a phase deviation signal and a phase advance-delay signal on the basis of the parallel phase information signal, in synchronization with the second clock signal;

a phase control amount processing circuit configured to generate a phase control signal on the basis of the phase deviation signal and the phase advance-delay signal and to output the phase control signal, the phase control signal being in synchronization with third clock signals having a frequency higher than that of the second clock signal; and

a phase interpolation circuit configured to adjust the phases of the third clock signals on the basis of the phase control signal, and to output the first clock signals as recovery clock signals.

2. The clock recovery circuit according to claim 1 , wherein the third clock signals are produced based on a reference clock signal.

3. The clock recovery circuit according to claim 1 , wherein the digital filtering circuit includes:

a phase tracking circuit configured to determine a direction of shift of the phases of the first clock signals based on the parallel phase information signal, and to generate the phase advance-delay signal representing an instantaneous advance or delay of the phases; and

a frequency tracking circuit configured to detect frequency deviation of the serial input signal from the first clock signals on the basis of the parallel phase information signal, and to generate the phase deviation signal representing the frequency deviation converted into a phase amount.

4. The clock recovery circuit according to claim 1 , wherein the phase control signal outputted from the phase control amount processing circuit is a string of thermometer codes.

5. The clock recovery circuit according to claim 4 , wherein the phase control amount processing circuit includes:

a shift amount determination circuit configured to generate a phase control amount on the basis of the phase deviation signal and the phase advance-delay signal, and to output the phase control amount in synchronization with the second clock signal, the phase control amount being represented by a parallel signal of consecutive “0” or “1”;

a shift register configured to output the phase control amount as a serial signal in synchronization with the first clock signals;

a phase control code generation circuit including a ring register in which data of consecutive “0” or “1” are stored in advance, and being configured to generate and output the phase control signal on the basis of the phase control amount; and

a shift direction determination circuit configured to determine a direction of shift in the ring register on the basis of the phase deviation signal and the phase advance-delay signal.

6. The clock recovery circuit according to claim 5 , wherein

the phase advance-delay signal includes a phase advance signal for advancing the phases of the first clock signals, and a phase delay signal for delaying the phases of the first clock signals, and

the shift direction determination circuit determines the shift direction in accordance with a result obtained by comparing the sum of “1”s included in the phase advance signal and the sum of “1”s included in the phase delay signal.

7. The clock recovery circuit according to claim 5 , wherein the phase control amount processing circuit further includes a phase quadrant code generation circuit having a ring register in which data of consecutive “1” or “0” are stored in advance, the phase quadrant code generation circuit being configured to generate a phase quadrant code representing a quadrant on which the phase control signal is located and to output the generated phase quadrant code to the phase interpolation circuit.

8. A data recovery circuit for recovering clock signal based on inputted serial signal and for recovering data of the inputted serial signal, comprising:

a plurality of samplers configured to sample a serial input signal in synchronization with a plurality of first clock signals having different phases respectively and to output a plurality of sampling data pieces;

a phase comparison circuit configured to output a serial phase information signal on the basis of the sampling data pieces, the serial phase information signal representing a phase relationship between a clock of the serial input signal and the different phases of the first clock signals;

a first serial-parallel conversion circuit configured to perform a serial-to-parallel conversion on the serial phase information signal in synchronization with a second clock signal having a frequency lower than that of the first clock signals, and to output a parallel phase information signal;

a digital filtering circuit configured to calculate a phase deviation signal and a phase advance-delay signal on the basis of the parallel phase information signal, in synchronization with the second clock signal;

a phase control amount processing circuit configured to generate a phase control signal on the basis of the phase deviation signal and the phase advance-delay signal and to output the phase control signal, the phase control signal being in synchronization with third clock signals having a frequency higher than that of the second clock signal;

a phase interpolation circuit configured to adjust the phases of the third clock signals on the basis of the phase control signal, and to output the first clock signals as recovery clock signals; and

a second serial-parallel circuit configured to perform a serial-to-parallel conversion on the sampled data pieces in synchronization with the first clock signals, and to output recovery data.

9. The data recovery circuit according to claim 8 , wherein the third clock signals are generated based on a reference clock signal.

10. The data recovery circuit according to claim 8 , wherein the digital filtering circuit includes:

a phase tracking circuit configured to determine a direction of shift of the phases of the first clock signals based on the parallel phase information signal, and to generate the phase advance-delay signal representing an instantaneous advance or delay of the phases; and

a frequency tracking circuit configured to detect frequency deviation of the serial input signal from the first clock signals on the basis of the parallel phase information signal, and to generate the phase deviation signal representing the frequency deviation converted into a phase amount.

11. The data recovery circuit according to claim 8 , wherein the phase control signal outputted from the phase control amount processing circuit is a string of thermometer codes.

12. The data recovery circuit according to claim 11 , wherein the phase control amount processing circuit includes:

a shift amount determination circuit configured to generate a phase control amount on the basis of the phase deviation signal and the phase advance-delay signal, and to output the phase control amount in synchronization with the second clock signal, the phase control amount being represented by a parallel signal of consecutive “0” or “1”;

a shift register configured to output the phase control amount as a serial signal in synchronization with the first clock signals;

a phase control code generation circuit including a ring register in which data of consecutive “0” or “1” are stored in advance, and being configured to generate and output the phase control signal on the basis of the phase control amount; and

a shift direction determination circuit configured to determine a direction of shift in the ring register on the basis of the phase deviation signal and the phase advance-delay signal.

13. The data recovery circuit according to claim 12 , wherein

the phase advance-delay signal includes a phase advance signal for advancing the phases of the first clock signals, and a phase delay signal for delaying the phases of the first clock signals, and

the shift direction determination circuit determines the shift direction in accordance with a result obtained by comparing the sum of “1”s included in the phase advance signal and the sum of “1”s included in the phase delay signal.

14. The data recovery circuit according to claim 12 , wherein the phase control amount processing circuit further includes a phase quadrant code generation circuit having a ring register in which data of consecutive “1” or “0” are stored in advance, the phase quadrant code generation circuit being configured to generate a phase quadrant code representing a quadrant on which the phase control signal is located and to output the generated phase quadrant code to the phase interpolation circuit.