Memory system
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data from stop of output of the Nth read clock and before a first predetermined time. The memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.
1. A memory system comprising:
a memory;
a memory controller; and
a memory interface electrically connecting the memory and the memory controller to each other, wherein
the memory interface includes a data line driven by the memory for transferring data, and a clock line which is driven by the memory controller and transfers read clocks for controlling a timing of outputting the data from the memory to the data line,
when the memory outputs N pieces of data, the memory starts outputting N pieces of data in synchronization with first to Nth read clocks consecutively output from the memory controller, stops the outputting of first to (N−1)th pieces of data respectively in synchronization with second to Nth read clocks, and stops the outputting of Nth piece of data after a first predetermined time from stop of output of the Nth read clock, and
the memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth read clocks, and takes in the Nth piece of data in a period from start of output of the Nth piece of data based on the Nth read clock to stop of the output of the Nth piece of data, and the memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.
2. The memory system according to claim 1 , wherein
when the memory outputs the N pieces of data, the memory starts outputting the N pieces of data within a second predetermined time from either one of falling edge and rising edge of each of the first to Nth read clocks consecutively output from the memory controller, stops the outputting of the first to (N−1)th pieces of data within a third predetermined time respectively from either one of falling edge and rising edge of each of the second to Nth read clocks, and stops the outputting of the Nth piece of data after the first predetermined time from stop of output of the Nth read clock.
3. The memory system according to claim 2 , wherein
the memory controller controls a cycle of the first to (N−1)th read clocks to be greater than a time obtained by subtracting the third predetermined time from the second predetermined time.
4. The memory system according to claim 2 , wherein
the memory controller controls a cycle of the first to (N−1)th read clocks to be smaller than a time twice the second predetermined time and to be greater than the second predetermined time.
5. The memory system according to claim 1 , wherein
the memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with either one of falling edge and rising edge of each of the second to Nth read clocks.
6. The memory system according to claim 1 , wherein
the memory controller takes in the Nth piece of data in synchronization with an edge at completion of output of the Nth read clock.
7. A memory system comprising:
a memory;
a memory controller; and
a memory interface electrically connecting the memory and the memory controller to each other, wherein
the memory interface includes a data line driven by the memory for transferring data, and a clock line which is driven by the memory controller and transfers read clocks for controlling a timing of outputting the data from the memory to the data line, and a return clock line for returning the read clock arrived at the memory via the clock line back to the memory controller as return read clock,
when the memory outputs N pieces of data, the memory starts outputting N pieces of data in synchronization with first to Nth read clocks consecutively output from the memory controller, stops the outputting of first to (N−1)th pieces of data respectively in synchronization with second to Nth read clocks, and stops the outputting of Nth piece of data after a first predetermined time from stop of output of the Nth read clock, and
the memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with second to Nth return read clocks, and takes in the Nth piece of data in a period from start of output of the Nth piece of data based on the Nth read clock to stop of the output of the Nth piece of data, and the memory controller sets an output period of the Nth read clock to be longer than an output period of each of the first to (N−1)th read clocks.
8. The memory system according to claim 7 , wherein
when the memory outputs the N pieces of data, the memory starts outputting the N pieces of data within a second predetermined time from either one of falling edge and rising edge of each of the first to Nth read clocks consecutively output from the memory controller, stops the outputting of the first to (N−1)th pieces of data within a third predetermined time respectively from either one of falling edge and rising edge of each of the second to Nth read clocks, and stops the outputting of the Nth piece of data after the first predetermined time from stop of output of the Nth read clock.
9. The memory system according to claim 8 , wherein
the memory controller controls a cycle of the first to (N−1)th read clocks to be greater than a time obtained by subtracting the third predetermined time from the second predetermined time.
10. The memory system according to claim 8 , wherein
the memory controller controls a cycle of the first to (N−1)th read clocks to be smaller than a time twice the second predetermined time and to be greater than the second predetermined time.
11. The memory system according to claim 7 , wherein
the memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with either one of falling edge and rising edge of each of the second to Nth return read clocks.
12. The memory system according to claim 7 , wherein
the memory controller takes in the Nth piece of data in synchronization with an edge at completion of output of the Nth read clock.