IP Library Granted Patent US 8,377,317
Granted Patent B2
US 8,377,317 · App. 12/853,304 · Granted Feb 19, 2013

Method for manufacturing printed circuit board with thick traces

Inventors: Yao-Wen Bai (Huaian, CN); Pan Tang (Huaian, CN); Xiao-Ping Li (Huaian, CN)
Assignees: Hong Heng Sheng Electrical Technology (HuaiAn) Co., Ltd; Zhen Ding Technology Co., Ltd.
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Quick Facts
Patent No.
US 8,377,317
App. No.
12/853,304
Granted
Feb 19, 2013
Kind
B2
Abstract

A method for manufacturing printed circuit board includes steps below. A first electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface is provided. A number of first traces directly formed on the second surface. A first insulating layer is formed on the second surface of the first electrically conductive layer and the surface of the first traces. The electrically conductive layer is etched to form a number of second traces, the second traces superpose the first traces, the first traces and the second traces constitute a circuit pattern.

Claims (27)

1. A method for manufacturing printed circuit board, comprising:

providing an electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface;

forming a plurality of first traces directly on the second surface of the electrically conductive layer;

attaching or printing an insulating layer directly on the second surface of the electrically conductive layer and the surface of the first traces after forming the plurality of first traces directly on the second surface of the electrically conductive layer; and

etching the electrically conductive layer to form a plurality of second traces conforming to the perimeter of the first traces after attaching or printing the insulating layer on the second surface of the electrically conductive layer and the surface of the first traces, the second traces superposed on the first traces, the first traces and the second traces cooperatively constituting a circuit pattern.

2. The method as claimed in claim 1 , further comprising a step of attaching a reinforcement sheet on the first surface of the electrically conductive layer prior to forming the first traces and a step of removing the reinforcement sheet prior to etching the electrically conductive layer to form the second traces.

3. The method as claimed in claim 1 , wherein the first traces are formed using an electro-plating process.

4. The method as claimed in claim 2 , wherein the first traces are formed by the steps comprising:

forming a photoresist layer on the second surface, and exposing and developing the photoresist layer to form a remaining patterned photoresist layer, with portions of the second surface of the electrically conductive layer being exposed; and

forming the first traces directly on the exposed portions of the second surface using a plating process.

5. The method as claimed in claim 3 , further comprising a step of removing the remaining patterned photoresist layer from the second surface after the first traces are formed.

6. The method as claimed in claim 1 , further comprising a step of forming a plating metal layer on the first surface of the electrically conductive layer prior to forming the first traces.

7. The method as claimed in claim 1 , wherein the electrically conductive layer is copper foil.

8. The method as claimed in claim 1 , further comprising a step of forming a solder mask layer on the circuit pattern to cover and protect the circuit pattern.

9. The method as claimed in claim 1 , wherein a thickness of the electrically conductive layer is in a range from 30 to 180 micrometers.

10. A method for manufacturing a printed circuit board comprising:

providing a first electrically conductive layer comprising a first surface and a second surface at an opposite side thereof to the first surface, and a second electrically layer having a third surface and a fourth surface at an opposite side thereof to the third surface;

forming a plurality of first traces directly on the second surface and a plurality of second traces directly on the fourth surface;

attaching the first electrically conductive layer and the second electrically conductive layer to opposite sides of an insulating layer after forming a plurality of first traces directly on the second surface and a plurality of second traces directly on the fourth surface, the second surface and fourth surface facing the insulating layer, the first traces and the second traces embedded in the insulating layer after plating the plurality of the first traces and the plurality second traces;

etching the first electrically conductive layer to form a plurality of third traces; and

etching the second electrically conductive layer to form a plurality of fourth traces after attaching the first electrically conductive layer and the second electrically conductive layer to opposite sides of an insulating layer, the third traces superposed on the first traces, the first traces and the third traces cooperatively constituting a first circuit pattern, the fourth traces superposed on the second traces, the second traces and the fourth traces cooperatively constituting a second circuit pattern.

11. The method as claimed in claim 10 , further comprising a step of attaching a first reinforcement sheet on the first surface and a second reinforcement sheet on the third surface prior to forming the first traces directly on the second surface and the second traces directly on the fourth surface, and steps of removing the first reinforcement sheet from the first surface and removing the second reinforcement sheet from the third surface.

12. The method as claimed in claim 10 , wherein the first traces and the second traces are formed using an electro-plating process.

13. The method as claimed in claim 10 , wherein the first traces and the second traces are formed by the steps comprising:

forming a first photoresist layer on the second surface, and exposing and developing the first phororesist layer to form a first remaining patterned photoresist with portions of the second surface of the first electrically conductive layer being exposed, forming a second photoresist layer on the fourth surface of the second electrically conductive layer, and exposing and developing the second phororesist layer to form a second remaining patterned photoresist layer with portions of the fourth surface of the second electrically conductive layer being exposed; and

forming the first traces directly on the expose portions of the second surface and the second traces directly on the exposed portions of the fourth surface using a plating process.

14. The method as claimed in claim 10 , further comprising forming a metal plating layer on the first surface prior to forming the third traces, and forming another metal plating layer on the third surface prior to forming the fourth traces.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE HONGQISHENG PRECISION ELECTRONICS CO., LTD., NO.18, TENGFEI ROAD, ECON. AND TECH. DEVELOPMENT ZONE, QINGUANGDAO, CHINA PREVIOUSLY RECORDED ON REEL 040978 FRAME 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 27, 2017
From: HONG HENG SHENG ELECTRONICAL TECHNOLOGY (HUAIAN) CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
To: HONG HENG SHENG ELECTRONICAL TECHNOLOGY (HUAIAN) CO., LTD.; GARUDA TECHNOLOGY CO., LTD
Reel/Frame 041951/0871 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2017
From: HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO.,LTD.; ZHEN DING TECHNOLOGY CO., LTD.
To: HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO.,LTD.; GARUDA TECHNOLOGY CO., LTD
Reel/Frame 040978/0400 →
CHANGE OF NAME Recorded Sep 13, 2011
From: FOXCONN ADVANCED TECHNOLOGY INC.
To: ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 026895/0137 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2010
From: BAI, YAO-WEN; TANG, PAN; LI, XIAO-PING
To: HONG HENG SHENG ELECTRONICAL TECHNOLOGY (HUAIAN)CO.,LTD; FOXCONN ADVANCED TECHNOLOGY INC.
Reel/Frame 024811/0149 →
Priority Claims (1)
CN 2010 1 0119553 · Mar 8, 2010 · national
Continuity (1)
Related Publication 20110215069A1 · Sep 8, 2011