Semiconductor device and method for manufacturing same
A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.
1. A semiconductor device comprising:
a compound semiconductor substrate;
an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and
a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer,
wherein the n-channel field-effect transistor region is a region that includes the p-type second channel layer; an n-type gate layer formed simultaneously with the n-type gate region; the first channel layer; and the n-type first barrier layer laminated in this order above the compound semiconductor substrate.
2. The semiconductor device according to claim 1 , wherein the p-channel field-effect transistor region is a region that includes the first channel layer, the n-type first barrier layer, and the second channel layer laminated in this order above the compound semiconductor substrate.
3. The semiconductor device according to claim 1 , further comprising a gate-leak prevention layer between the n-type gate region and the p-type second channel layer.
4. The semiconductor device according to claim 3 , wherein the p-type second channel layer includes p-type source and drain regions formed as Zn-diffused layers, and that are separated from each other with the n-type gate region in between.
5. The semiconductor device according to claim 4 , further comprising an n-type second barrier layer formed between the compound semiconductor substrate and the first channel layer, and that supplies an n-type charge to the first channel layer.
6. The semiconductor device according to claim 5 , wherein the p-channel field-effect transistor region includes a backgate electrode.
7. The semiconductor device according to claim 1 , wherein the p-type second channel layer includes p-type source and drain regions formed as Zn-diffused layers, and that are separated from each other with the n-type gate region in between.
8. The semiconductor device according to claim 1 , further comprising an n-type second barrier layer formed between the compound semiconductor substrate and the first channel layer, and that supplies an n-type charge to the first channel layer.
9. The semiconductor device according to claim 1 , wherein the p-channel field-effect transistor region includes a backgate electrode.
10. A semiconductor device comprising:
a compound semiconductor substrate;
an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and
a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer,
wherein the p-channel field-effect transistor region includes a backgate electrode, and
wherein the backgate electrode of the p-channel field-effect transistor is formed on the n-type first barrier layer.
11. A semiconductor device manufacturing method, comprising the steps of:
forming a multilayered film by the sequential epitaxial growth of a first buffer layer, a first channel layer, an n-type first barrier layer, a second buffer layer, a p-type second channel layer, and an n-type gate layer on a compound semiconductor substrate;
selectively removing the n-type gate layer to form an n-type gate region for a p-channel field-effect transistor;
selectively removing the p-type second channel layer so as to lay out a p-channel field-effect transistor region in which the p-type second channel layer remains with the n-type gate region, and an n-channel field-effect transistor region in which the n-type first barrier layer remains;
forming an insulating film simultaneously on exposed surfaces of the p-channel field-effect transistor region and the n-channel field-effect transistor region, and forming first opening portions through the insulating film;
diffusing Zn impurities through the first opening portions to simultaneously form source and drain regions for the p-channel field-effect transistor, and a gate region for an n-channel field-effect transistor;
forming an element isolation region that electrically separates the p-channel field-effect transistor region and the n-channel field-effect transistor region from each other; and
forming a metal electrode in the source and drain regions for the p-channel field-effect transistor, and in the gate region for the n-channel field-effect transistor.
12. The method according to claim 11 , further comprising the step of forming a backgate electrode for the p-channel field-effect transistor on the n-type first barrier layer simultaneously when forming a metal electrode in source and drain regions for the n-channel field-effect transistor.
13. A semiconductor device manufacturing method, comprising the steps of:
forming a multilayered film by the sequential epitaxial growth of a first buffer layer, a p-type second channel layer, an n-type gate layer, an n-type second barrier layer, a first channel layer, and an n-type first barrier layer on a compound semiconductor substrate;
forming an element isolation region that electrically separates a p-channel field-effect transistor region and an n-channel field-effect transistor region from each other;
selectively removing the n-type first barrier layer, the first channel layer, and the n-type second barrier layer of the p-channel field-effect transistor region;
selectively removing the n-type gate layer of the p-channel field-effect transistor region to form an n-type gate region for a p-channel field-effect transistor;
forming an insulating film simultaneously on exposed surfaces of the p-channel field-effect transistor region and the n-channel field-effect transistor region, and forming opening portions through the insulating film;
diffusing Zn impurities through the opening portions to simultaneously form source and drain regions for the p-channel field-effect transistor, and a gate region for an n-channel field-effect transistor; and
forming a metal electrode in the source and drain regions for the p-channel field-effect transistor, and in the gate region for the n-channel field-effect transistor.
14. The method according to claim 13 , further comprising the step of forming a backgate electrode for the p-channel field-effect transistor on the n-type first barrier layer simultaneously when forming a metal electrode in source and drain regions for the n-channel field-effect transistor.