Three-dimensional semiconductor memory device and method of fabricating the same
A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.
1. A method of fabricating a semiconductor memory device, comprising:
alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate;
forming an active pattern on the substrate, such that the active pattern penetrates the sacrificial layers and the insulating layers;
continuously patterning the insulating layers and the sacrificial layers to form a trench;
removing the sacrificial layers exposed in the trench to form recess regions, such that the recess regions expose a sidewall of the active pattern;
forming an information storage layer on the substrate;
depositing a gate conductive layer on the information storage layer, such that the deposited gate conductive layer completely fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer; and
performing an isotropic etch process with respect to the deposited gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.
2. The method as claimed in claim 1 , wherein depositing the gate conductive layer to define the empty region in the trench includes defining a bottom surface of the empty region by the gate conductive layer, such that the bottom surface of the empty region is lower than a top surface of a portion of the gate conductive layer filling a lowermost recess region among the recess regions.
3. The method as claimed in claim 1 , wherein forming the gate electrodes in the recess regions includes recessing sidewalls of the gate electrodes adjacent to the trench further laterally than sidewalls of the patterned insulating layers adjacent to the trench by the isotropic etch process.
4. The method as claimed in claim 3 , further comprising forming a device isolation pattern filling the trench and portions of the recess regions adjacent to the gate electrodes.
5. The method as claimed in claim 1 , wherein patterning the insulating layers and the sacrificial layers to form a trench includes forming the trench with an oblique sidewall, such that a width of a lower end of the trench is smaller than a width of an upper end of the trench.
6. The method as claimed in claim 5 , wherein forming the gate electrodes includes forming a width of an uppermost gate electrode among the gate electrodes smaller than a width of a lowermost gate electrode.
7. The method as claimed in claim 1 , wherein forming the active pattern includes:
forming a channel opening penetrating the insulating layers and the sacrificial layers to expose the substrate; and
forming the active pattern in the channel opening, such that the trench is spaced apart laterally from the channel opening.
8. The method as claimed in claim 7 , wherein forming the active pattern in the channel opening includes:
conformally forming an active layer on the substrate having the channel opening;
forming a dielectric on the active layer to fill the channel opening; and
removing portions of the dielectric and the active layer outside the channel opening.
9. The method as claimed in claim 1 , further comprising forming a common source region in the substrate below the trench.
10. The method as claimed in claim 1 , further comprising:
forming a drain region in an upper portion of the active pattern; and
forming a bit line electrically connected to the drain region.
11. The method as claimed in claim 1 , further comprising, prior to stacking the sacrificial layers and the insulating layers, forming a buffer dielectric on the substrate, such that a lowermost sacrificial layer among the sacrificial layers is formed directly on the buffer dielectric.
12. The method as claimed in claim 1 , wherein prior to performing the isotropic etch process, the deposited gate conductive layer is a continuous layer, and during the isotropic etch process the deposited gate conductive layer is separated into the gate electrodes.
13. A method of fabricating a semiconductor memory device, comprising:
alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate;
forming an active pattern on the substrate, such that the active pattern penetrates the sacrificial layers and the insulating layers;
continuously patterning the insulating layers and the sacrificial layers to form a trench;
removing the sacrificial layers exposed in the trench to form recess regions, such that the recess regions expose a sidewall of the active pattern;
forming an information storage layer on the substrate;
forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer; and
performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions such that the gate electrodes are separated from each other, forming the gate electrodes in the recess regions including recessing sidewalls of the gate electrodes adjacent to the trench further laterally than sidewalls of the patterned insulating layers adjacent to the trench by the isotropic etch process.
14. The method as claimed in claim 13 , further comprising forming a device isolation pattern filling the trench and portions of the recess regions adjacent to the gate electrodes.
15. A method of fabricating a semiconductor memory device, comprising:
alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate;
forming an active pattern on the substrate, such that the active pattern penetrates the sacrificial layers and the insulating layers;
continuously patterning the insulating layers and the sacrificial layers to form a trench, the trench being formed with an oblique sidewall such that a width of a lower end of the trench is smaller than a width of an upper end of the trench;
removing the sacrificial layers exposed in the trench to form recess regions, such that the recess regions expose a sidewall of the active pattern;
forming an information storage layer on the substrate;
forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer; and
performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions such that the gate electrodes are separated from each other, forming the gate electrodes including forming a width of an uppermost gate electrode among the gate electrodes smaller than a width of a lowermost gate electrode.
16. The method as claimed in claim 15 , wherein forming the gate conductive layer to define the empty region in the trench includes defining a bottom surface of the empty region by the gate conductive layer, such that the bottom surface of the empty region is lower than a top surface of a portion of the gate conductive.
17. The method as claimed in claim 15 , wherein forming the gate electrodes in the recess regions includes recessing sidewalls of the gate electrodes adjacent to the trench further laterally than sidewalls of the patterned insulating layers adjacent to the trench by the isotropic etch process.