IP Library Granted Patent US 8,383,949
Granted Patent B2
US 8,383,949 · App. 12/649,328 · Granted Feb 26, 2013

Method to form lateral pad on edge of wafer

Inventors: Edris M. Mohammed (Beaverton, OR); Hinmeng Au (San Jose, CA)
Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,383,949
App. No.
12/649,328
Granted
Feb 26, 2013
Kind
B2
Abstract

Embodiments are directed to an apparatus and fabrication method to form pad arrays on the edge of a substrate wafer substrate. Embodiments of the invention make it possible for surface mount devices to be bonded vertically (i.e. on their side) using standard semiconductor assembly processes.

Claims (18)

1. A component, comprising:

a dielectric wafer portion comprising a plurality of metal filled trenches;

a plurality of metal traces on the dielectric wafer portion crossing over the plurality of metal filled trenches;

a lateral side of the component including an exposed cross-section of the metal filled trench, wherein the cross-section of each metal filled trench is a bonding pad when the component is turned on its side; and

a glass layer on the dielectric wafer portion wherein the metal filled trench bonding pad is sandwiched beneath and between the glass layer and the dielectric wafer portion.

2. The component as recited in claim 1 further comprising:

a plurality of said dielectric wafers stacked one on top of the other, wherein the cross-sections of the metal filled trenches comprise a bonding pad array.

3. The component as recited in claim 1 wherein the component is vertically flip-chip bonded to a substrate using the bonding pads.

4. The component as recited in claim 1 wherein the exposed cross-section of the metal filled trench has a roughness Ra of about 0.2 um.

5. A component, comprising:

a dielectric wafer portion comprising a plurality of metal filled trenches;

a plurality of metal traces on the dielectric wafer portion crossing over the plurality of metal filled trenches;

a lateral side of the component including an exposed cross-section of the metal filled trench, wherein the cross-section of each metal filled trench is a bonding pad when the component is turned on its side; and

a plastic layer on the dielectric wafer portion wherein the metal filled trench bonding pad is sandwiched beneath and between the plastic layer and the dielectric wafer portion.

6. The component as recited in claim 5 further comprising:

a plurality of said dielectric wafers stacked one on top of the other, wherein the cross-sections of the metal filled trenches comprise a bonding pad array.

7. The component as recited in claim 5 wherein the component is vertically flip-chip bonded to a substrate using the bonding pads.

8. The component as recited in claim 5 wherein the exposed cross-section of the metal filled trench has a roughness Ra of about 0.2 um.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2012
From: MOHAMMED, EDRIS M.; AU, HINMENG
To: INTEL CORPORATION
Reel/Frame 029223/0072 →
Continuity (1)
Related Publication 20110155435A1 · Jun 30, 2011