Semiconductor memory device with security function and control method thereof

1. A semiconductor memory device comprising:

a storage block having a storage region configured to store data, wherein the storage region is enabled to allow data to be written therein if an unlock status is associated with the storage region and disabled to prevent data from being written therein if a lock status is associated with the storage region, when a program command is input; and

a controller configured to prevent the lock status from being changed to the unlock status,.

wherein the storage block includes:

a one time programmable (OTP) register configured to store the data, the storage region being the OTP register; and

an OTP lock register configured to store information indicating the lock/unlock status of the OTP register, and

wherein the controller includes:

an address comparator configured to compare an external input address with an address of the OTP lock register, and output a comparison signal;

a program pulse generating unit configured to output a reset pulse and a set pulse in response to the comparison signal; and

a read signal generating unit configured to output a read control signal in response to the comparison signal.

2. The semiconductor memory device according to claim 1 , wherein each of the OTP register and the OTP lock register includes:

a plurality of unit cells in a cell array.

3. The semiconductor memory device according to claim 2 , further comprising:

a write driver configured to write or program data in one or more of the unit cells.

4. The semiconductor memory device according to claim 1 , wherein the program pulse generating unit is configured to disable the reset pulse when the external input address and the address of the OTP lock register correspond to each other.

5. The semiconductor memory device according to claim 1 , wherein the program pulse generating unit includes:

a reset pulse generator configured to generate the reset pulse;

a logic gate configured to output a control signal to activate the reset pulse generator when the program command is input and the external input address is different from the address of the OTP lock register; and

a set pulse generator configured to be activated by the program command to generate the set pulse.

6. The semiconductor memory device according to claim 1 , wherein the read signal generating unit is configured to disable the read control signal when the external input address is identical to the address of the OTP lock register.

7. The semiconductor memory device according to claim 1 , wherein the read signal generating unit includes:

a read signal generator configured to generate the read control signal; and

a logic gate configured to activate the read signal generator when a read command is input and the external input address is different from the address of the OTP lock register.

8. The semiconductor memory device according to claim 1 , wherein the lock status represents a status that a specific operation for changing the data stored in the storage block is prohibited, and wherein the storage block includes one or more non-volatile memory cells.

9. A method for controlling a semiconductor memory device, the method comprising:

providing a storage block having a storage region configured to store data, wherein the storage region is associated with a lock/unlock status;

determining whether or not a program command that is input indicates the lock/unlock status is to be changed; and

prohibiting a lock status from being changed to an unlock status before the determining step when the program command is input,

wherein prohibiting the lock status from being changed to the unlock status includes:

comparing an external input address with an address corresponding to the data in the lock status when the program command is input; and

prohibiting the change of the lock status of the data according to a result of the comparison.

10. The method according to claim 9 , further comprising:

enabling the change to the unlock status of the data if the external input address is different from the address corresponding to the data in the lock status.

11. The method according to claim 9 , wherein the determining step includes:

confirming information indicating a lock/unlock status of a one time programmable (OTP) register corresponding to the external input address, wherein the OTP register stores the data.

12. A phase-change memory device comprising:

a register configured to include a plurality of phase-change memory cells;

a lock register configured to store information indicating a lock/unlock status of each phase-change memory cell;

a write driver configured to generate a program current for programming the plurality of phase-change memory cells; and

a controller configured to control the write driver to prevent the program current from being provided to one or more phase-change memory cells in a lock status among the plurality of phase-change memory cells.

13. The phase-change memory device according to claim 12 , wherein the lock register stores addresses of the one or more phase-change memory cells in the lock status.

14. The phase-change memory device according to claim 13 , wherein, in a write operation, the controller is configured to compare an address of each phase-change memory cell in the lock status with a programming address provided from an external device, and cause the write driver not to provide the program current to the phase-change memory cell in the lock status when the address of the phase-change memory cell in the lock status and the programming address provided from the external device are identical to each other.

15. The phase-change memory device according to claim 12 , wherein the lock register stores addresses of one or more phase-change memory cells in an unlock status among the plurality of phase-change memory cells.

16. The phase-change memory device according to claim 13 , wherein in a write operation, the controller is configured to compare an address of each phase-change memory cell in the unlock status with a programming address provided from an external device, and cause the write driver to provide the program current to the phase-change memory cell in the unlock status when the address of the phase-change memory cell in the lock status and the programming address provided from the external device are identical to each other.

17. The phase-change memory device according to claim 12 , wherein the lock register includes one or more non-volatile memory cells.

18. A control method of a semiconductor memory device comprising:

verifying whether a programming command is to program an OTP lock register or an OTP register;

reading the OTP lock register when the programming command is to program the OTP register;

verifying whether information stored in the OTP lock register is in a lock status or in a unlock status; and

programming the OTP register and the OTP lock register according to the programming command,

wherein verifying whether the programming command is to program the OTP lock register or the OTP register includes:

comparing an external input address of the programming command with an address of the OTP lock register.

19. The control method according to claim 18 , further comprising:

preventing a unlock status data from being programmed in the OTP lock register when the programming command is to program the OTP lock register.

20. The control method according to claim 18 , wherein the OTP register and the OTP lock register are programmed when the information stored in the OTP lock register is in the unlock status.