IP Library Granted Patent US 8,389,406
Granted Patent B2
US 8,389,406 · App. 12/656,629 · Granted Mar 5, 2013

Method of manufacturing semiconductor device

Inventors: Hideyuki Sameshima (Tokyo, JP); Tomoo Ono (Tokyo, JP)
Assignee: Lapis Semiconductor Co., Ltd.
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Quick Facts
Patent No.
US 8,389,406
App. No.
12/656,629
Granted
Mar 5, 2013
Kind
B2
Abstract

There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.

Claims (42)

1. A method of manufacturing a semiconductor device, the method comprising:

preparing a semiconductor substrate formed with an electrode pad on a main surface side;

forming a first insulating layer from an insulating material so as to cover the electrode pad and the semiconductor substrate, the first insulating layer provided with a first opening through which a portion of the electrode pad is exposed;

forming a first redistribution layer on the first opening and on the first insulating layer from a first electrically conductive material;

forming a second insulating layer from an insulating material, the second insulating layer provided with a second opening through which a portion of the first redistribution layer that is superimposed on the first opening is exposed, and the second insulating layer being formed so as to cover portions of the first redistribution layer other than those of the second opening and to cover the first insulating layer;

forming a second redistribution layer on the second opening and on the second insulating layer from a second electrically conductive material; and

first processing when forming the first redistribution layer, in which, the first electrically conductive material is filled in the first opening to form a via interconnect and thereafter the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the via interconnect, wherein the first processing includes

forming a first electrically conductive layer containing the first electrically conductive material so as to cover the electrode pad and the first insulating layer,

forming a resist film on the first electrically conductive layer other than in a region where the first opening is formed,

filling the first electrically conductive material in the first opening to form the via interconnect by growing the first electrically conductive material using an electroplating method until a surface of the first electrically conductive material becomes higher than a surface of the first insulating layer,

removing a part of the resist film to leave a remainder part of the resist film such that the first electrically conductive layer is exposed from the resist film in a region where the first redistribution layer is to be formed, and

growing, in the exposed region, the first electrically conductive material on the first electrically conductive layer using an electroplating method to form the first redistribution layer to electrically connect to the via interconnect.

2. The method of claim 1 , wherein the first processing comprising:

depositing the first electrically conductive material so as to cover the electrode pad and the first insulating layer up to a height of the surface of the first insulating layer or higher;

forming a resist film on the deposited film corresponding to the first opening;

forming the via interconnect by employing the resist film to remove the first electrically conductive material on the surface of the first insulating layer; and

forming the first redistribution layer electrically connected to the via interconnect by depositing the first electrically conductive material on the first insulating layer and on the via interconnect.

3. The method of claim 2 wherein the first electrically conductive material is deposited by sputtering.

4. The method of claim 1 , wherein the first electrically conductive material and the second electrically conductive material each comprises copper.

5. The method of claim 1 , further comprising second processing when forming the second redistribution layer, in which, the second electrically conductive material is filled in the second opening to form a second via interconnect and thereafter the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.

6. The method of claim 5 , wherein the second processing comprises:

depositing the second electrically conductive material so as to cover the first redistribution layer and the first insulating layer up to the height of the surface of the second insulating layer or higher;

forming a resist film on the deposited film corresponding to the second opening;

forming the second via interconnect by employing the resist film to remove the second electrically conductive material on the surface of the second insulating layer; and

forming the second redistribution layer electrically connected to the second via interconnect by depositing the second electrically conductive material on the second insulating layer and on the second via interconnect.

7. The method of claim 1 , wherein the growing of the first electrically conductive material in the exposed region includes growing the first electrically conductive material between portions of the remainder part of the resist film.

8. A method of manufacturing a semiconductor device, the method comprising:

preparing a semiconductor substrate formed with an electrode pad on a main surface side;

forming a first insulating layer from an insulating material so as to cover the electrode pad and the semiconductor substrate, the first insulating layer provided with a first opening through which a portion of the electrode pad is exposed;

forming a first redistribution layer on the first opening and on the first insulating layer from a first electrically conductive material;

forming a second insulating layer from an insulating material, the second insulating layer provided with a second opening through which a portion of the first redistribution layer that is superimposed on the first opening is exposed, and the second insulating layer being formed so as to cover portions of the first redistribution layer other than those of the second opening and to cover the first insulating layer;

forming a second redistribution layer on the second opening and on the second insulating layer from a second electrically conductive material; and

processing when forming the second redistribution layer, in which, the second electrically conductive material is filled in the second opening to form a via interconnect and thereafter the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the via interconnect,

wherein the processing includes

forming a second electrically conductive layer containing the second electrically conductive material so as to cover the first redistribution layer and the second insulating layer,

forming a resist film on the second electrically conductive layer other than in a region where the second opening is formed,

filling the second electrically conductive material in the second opening to form the via interconnect by growing the second electrically conductive material using an electroplating method until a surface of the second electrically conductive material becomes higher than a surface of the second insulating layer,

removing a part of the resist film to leave a remainder part of the resist film such that the second electrically conductive layer is exposed from the resist film in a region where the second redistribution layer is to be formed, and

growing, in the exposed region, the second electrically conductive material on the second electrically conductive layer using an electroplating method to form the second redistribution layer to electrically connect to the via interconnect.

9. The method of claim 8 , wherein the first electrically conductive material and the second electrically conductive material each comprises copper.

10. The method of claim 8 , further comprising another processing when forming the first redistribution layer, in which, the first electrically conductive material is filled in the first opening to form another via interconnect and thereafter the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the another via interconnect.

11. The method of claim 8 , wherein the growing of the second electrically conductive material in the exposed region includes growing the second electrically conductive material between portions of the remainder part of the resist film.

Assignments (2)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2010
From: SAMESHIMA, HIDEYUKI; ONO, TOMOO
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 023968/0252 →
Priority Claims (1)
JP 2009-032035 · Feb 13, 2009 · national
Continuity (1)
Related Publication 20100210103A1 · Aug 19, 2010