IP Library Granted Patent US 8,390,326
Granted Patent B2
US 8,390,326 · App. 12/782,448 · Granted Mar 5, 2013

Method for fabrication of a semiconductor element and structure thereof

Inventors: Zvi Or-Bach (San Jose, CA); James M. Tour (Bellaire, TX); Jun Yao (Houston, TX); Brian Cronquist (San Jose, CA)
Assignee: William Marsh Rice University
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Quick Facts
Patent No.
US 8,390,326
App. No.
12/782,448
Granted
Mar 5, 2013
Kind
B2
Abstract

Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Additionally, the re-programmable antifuses may be configured to a permanently conductive state by applying an even higher voltage across it.

Claims (58)

1. An integrated circuit device comprising:

a configurable interconnect circuit comprising at least one antifuse;

wherein the at least one antifuse is configured to be programmed to be conducting by applying a first voltage across it and is configured to be re-programmed to be non-conducting by applying second voltage across it; and

wherein the at least one antifuse is further configured to be permanently conducting by applying a third voltage across it;

wherein the third voltage is higher than the first voltage or the second voltage.

2. The integrated circuit device of claim 1 , wherein the configurable interconnect circuit further comprises:

a first layer of conductive first strips;

an insulation layer; and

a second layer of conductive second strips;

wherein the conductive second strips are arranged in a substantially perpendicular orientation to the conductive first strips.

3. The integrated circuit device of claim 2 , wherein the insulation layer includes the at least one antifuse; and

wherein the at least one antifuse is in a region directly above the conductive first strips and directly below the conductive second strips.

4. The integrated circuit device of claim 3 , wherein the at least one antifuse comprises SiO x ; and

wherein x has a value higher than 1 and less than or equal to 2.

5. The integrated circuit device of claim 3 , wherein the at least one antifuse comprises more than one layer of SiO x ;

wherein x has a value higher than 1 and less than or equal to 2; and

wherein the value of x is not the same in each layer of SiO x .

6. The integrated circuit device of claim 3 , wherein the at least one antifuse comprises carbon.

7. The integrated circuit device of claim 6 , wherein the at least one antifuse further comprises a sacrificial layer.

8. The integrated circuit device of claim 2 , wherein the second layer of conductive second strips further comprises at least one strip of re-programmable antifuse oriented substantially perpendicular with respect to the conductive second strips.

9. The integrated circuit device of claim 8 , wherein the at least one strip of re-programmable antifuse comprises SiO x ;

wherein x has a value higher than 1 and less than or equal to 2.

10. The integrated circuit device of claim 8 , wherein the at least one strip of re-programmable antifuse comprises more than one layer of SiO x ;

wherein x has a value higher than 1 and less than or equal to 2; and

wherein the value of x is not the same in each layer of SiO x .

11. The integrated circuit device of claim 8 , wherein the at least one strip of re-programmable antifuse comprises carbon.

12. The integrated circuit device of claim 11 , wherein the at least one strip of re-programmable antifuse further comprises a sacrificial layer.

13. The integrated circuit device of claim 1 , wherein the second voltage is higher than the first voltage.

14. An integrated circuit device comprising:

a configurable interconnect circuit arranged to be configurable by at least one antifuse;

wherein the at least one antifuse is configured to be activated by applying a first voltage across it and to be programmed to be conducting by then applying a second voltage across it;

wherein the at least one antifuse is further configured be re-programmed to be non-conducting by applying a third voltage across it; and

wherein the at least one antifuse is further configured to be permanently conducting by applying a fourth voltage across it;

wherein the fourth voltage is higher than the first voltage, the second voltage or the third voltage.

15. The integrated circuit device of claim 14 , wherein the configurable interconnect circuit further comprises:

a first layer of conductive first strips;

an insulation layer; and

a second layer of conductive second strips;

wherein the conductive second strips are arranged in a substantially perpendicular orientation with respect to the conductive first strips.

16. The integrated circuit device of claim 15 , wherein the insulation layer includes the at least one antifuse; and

wherein the at least one antifuse is in a region directly above the conductive first strips and directly below the conductive second strips.

17. The integrated circuit device of claim 16 , wherein the at least one antifuse comprises SiO x ; and

wherein x has a value higher than 1 and less than or equal to 2.

18. The integrated circuit device of claim 16 , wherein the at least one antifuse comprises more than one layer of SiO x ;

wherein x has a value higher than 1 and less than or equal to 2; and

wherein the value of x is not the same in each layer of SiO x .

19. The integrated circuit device of claim 16 , wherein the at least one antifuse comprises carbon.

20. The integrated circuit device of claim 19 , wherein the at least one antifuse further comprises a sacrificial layer.

21. The integrated circuit device of claim 15 , wherein the second layer further comprises at least one strip of re-programmable antifuse oriented substantially perpendicular with respect to the conductive second strips.

22. The integrated circuit device of claim 21 , wherein the at least one strip of re-programmable antifuse comprises SiO x ;

wherein x has a value higher than 1 and less than or equal to 2.

23. The integrated circuit device of claim 21 , wherein the at least one re-programmable antifuse comprises more than one layer of SiO x ;

wherein x has a value higher than 1 and less than or equal to 2; and

wherein the value of x is not the same in each layer of SiO x .

24. The integrated circuit device of claim 21 , wherein the at least one strip of re-programmable antifuse comprises carbon.

25. The integrated circuit device of claim 24 , wherein the at least one strip of re-programmable antifuse further comprises a sacrificial layer.

26. The integrated circuit device of claim 14 , wherein the first voltage is higher than the third voltage; and

wherein the third voltage is higher than the second voltage.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME CHANGED FROM MONOLITHIC 3D TO MONOLITHIC 3D INC. PREVIOUSLY RECORDED ON REEL 027798 FRAME 0063. ASSIGNOR(S) HEREBY CONFIRMS THE ENTIRE ENTRY. Recorded Mar 9, 2012
From: OR-BACH, ZVI; CRONQUIST, BRIAN
To: MONOLITHIC 3D INC.
Reel/Frame 027839/0239 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2012
From: OR-BACH, ZVI; CRONQUIST, BRIAN
To: MONOLITHIC 3D
Reel/Frame 027798/0063 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2011
From: TOUR, JAMES M.; YAO, JUN
To: WILLIAM MARSH RICE UNIVERSITY
Reel/Frame 026261/0438 →
CONFIRMATORY LICENSE Recorded Jan 3, 2011
From: RICE UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 025574/0076 →
Continuity (2)
Continuation In Part 12435661 · May 5, 2009
Related Publication 20100289524A1 · Nov 18, 2010