Image display system and gate driver circuit
An image display system includes a gate driving circuit. The gate driving circuit includes several stages of gate drivers each for generating a gate driving signal to drive a row of pixels. Each stage of the gate driver receives a clock signal and a first reset signal. A first stage of the gate driver receives a vertical start pulse as an input signal of the first stage. The remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver as the input signal of the remaining stages. Each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver as a second reset signal, and generates the corresponding gate driving signal according to the clock signal, the first reset signal, and the corresponding input signal and second reset signal.
1. An image display system, comprising:
a gate driver circuit, comprising:
a plurality of stages of gate drivers, each for generating a gate driving signal to drive a row of pixels in a pixel array,
wherein each stage of the gate driver circuit receives a clock signal and a first reset signal, a first stage of the gate driver circuit receives a vertical start pulse as an input signal of the first stage, the remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver circuit as the corresponding input signal of the remaining stages, and each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver circuit as a second reset signal, and
wherein each stage of the gate driver comprises:
an input circuit, comprising a first transistor directly coupled between a first supply voltage and a node and receiving the input signal;
a reset circuit, directly coupled to the node and generating a control signal at the node, wherein the reset circuit comprises:
a second transistor, directly coupled between a second supply voltage and the node and receiving the first reset signal; and
a third transistor, directly coupled between the second supply voltage and the node and receiving the second reset signal,
wherein the first transistor, the second transistor and the third transistor are turned on or off according to the input signal, the first reset signal and the second reset signal, respectively, and the control signal is generated at the node according to the first supply voltage and the second supply voltage;
a storage circuit, directly coupled to the node and comprising a latch for storing the control signal; and
an output circuit, directly coupled to the storage circuit and comprising:
a fourth transistor, having a first terminal receiving the control signal and a second terminal receiving the clock signal; and
a fifth transistor, having a first terminal receiving the control signal and a second terminal directly coupled to the second supply voltage,
wherein the fourth transistor and the fifth transistor are respectively turned on or off according to the control signal, and the gate driving signal is generated according to the clock signal and the second supply voltage.
2. The image display system as claimed in claim 1 , further comprising a display panel, wherein the display panel comprises:
the gate driver circuit;
the pixel array; and
a controller chip, for generating the clock signal, the first reset signal and the vertical start pulse.
3. The image display system as claimed in claim 2 , further comprising an electronic device, wherein the electronic device comprises:
the display panel; and
an input device, receiving signals to control the display panel to display images.
4. The image display system as claimed in claim 3 , wherein the electronic device is a mobile phone, a digital camera, a personal digital assistant (PDA), a lap-top computer, a personal computer, a television, a vehicle displayer, or a portable DVD player.
5. The image display system as claimed in claim 1 , wherein the reset circuit resets the control signal during a first time period according to the first reset signal and the second supply voltage, and resets the control signal during a second time period according to the second reset signal and the second supply voltage.
6. A gate driver circuit, comprising:
a plurality of stages of gate drivers, each for generating a gate driving signal to drive a row of pixels in a pixel array,
wherein each stage of the gate driver circuit receives a clock signal and a first reset signal, a first stage of the gate driver circuit receives a vertical start pulse as an input signal of the first stage, the remaining stages of the gate drivers respectively receive the gate driving signal generated by a previous stage of the gate driver circuit as the input signal of the remaining stages, and each stage of the gate drivers further receives the gate driving signal generated by a next stage of the gate driver circuit as a second reset signal, and
wherein each stage of the gate driver comprises:
an input circuit, comprising a first transistor directly coupled between a first supply voltage and a node and receiving the input signal;
a reset circuit, directly coupled to the node and generating a control signal at the node, wherein the reset circuit comprises:
a second transistor, directly coupled between a second supply voltage and the node and receiving the first reset signal; and
a third transistor, directly coupled between the second supply voltage and the node and receiving the second reset signal,
wherein the first transistor, the second transistor and the third transistor are turned on or off according to the input signal, the first reset signal and the second reset signal, respectively, and the control signal is generated at the node according to the first supply voltage and the second supply voltage;
a storage circuit, directly coupled to the node and comprising a latch for storing the control signal; and
an output circuit, directly coupled to the storage circuit and comprising:
a fourth transistor, having a first electrode receiving the control signal and a second electrode receiving the clock signal; and
a fifth transistor, having a first electrode receiving the control signal and a second electrode directly coupled to the second supply voltage,
wherein the fourth transistor and the fifth transistor are respectively turned on or off according to the control signal and the gate driving signal is generated according to the clock signal and the second supply voltage.
7. The gate driver circuit as claimed in claim 6 , wherein the gate driver circuit is comprised in a display panel, and the display panel further comprises:
the pixel array; and
a controller chip, for generating the clock signal, the first reset signal and the vertical start pulse.
8. The gate driver circuit as claimed in claim 7 , wherein the display panel is comprised in an electronic device, and the electronic device comprises:
an input device, receiving signals to control the display panel to display images.
9. The gate driver circuit as claimed in claim 8 , wherein the electronic device is a mobile phone, a digital camera, a personal digital assistant (PDA), a lap-top computer, a personal computer, a television, a vehicle displayer, or a portable DVD player.
10. The gate driver circuit as claimed in claim 6 , wherein the reset circuit resets the control signal during a first time period according to the first reset signal and the second supply voltage, and resets the control signal during a second time period according to the second reset signal and the second supply voltage.