Method of manufacturing and assembling semiconductor chips with offset pads
A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.
1. A method of assembling a semiconductor chip device, comprising:
stacking a first semiconductor chip with a second semiconductor chip, the first semiconductor chip including a first edge, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and
wherein the first semiconductor chip includes a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.
2. The method of claim 1 , wherein the first semiconductor chip comprises an interposer.
3. The method of claim 1 , wherein each of the first and second conductor pillars comprises an end and a solder structure positioned on the end.
4. The method of claim 1 , wherein the first conductor structure is coupled to the first conductor pillar and the second conductor structure is coupled to the second conductor pillar.
5. The method of claim 4 , wherein the first and second conductor structures comprise conductor pillars.
6. The method of claim 5 , wherein each of the first and second conductor structures comprises an end and a solder structure positioned on the end.
7. The method of claim 1 , comprising coupling the first and second semiconductor chips to a circuit board.
8. A method of manufacturing, comprising:
fabricating a first semiconductor chip adapted to be stacked with a second semiconductor chip, the first semiconductor chip including a first edge, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and
forming a first conductor pad on the first semiconductor chip;
forming a first conductor pillar on but laterally offset from the first conductor pad toward the first edge and with a first lateral dimension and being adapted to couple to one of the first and second conductor structures;
forming a second conductor pad on the first semiconductor chip positioned nearer the first edge than the first conductor pad; and
forming a second conductor pillar on but laterally offset from the second conductor pad and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.
9. The method of claim 8 , wherein the first semiconductor chip comprises an interposer.
10. The method of claim 8 , wherein each of the first and second conductor pillars comprises an end, the method comprising placing a solder structure on each of the ends.
11. The method of claim 8 , comprising coupling the first conductor structure to the first conductor pillar and the second conductor structure to the second conductor pillar.
12. The method of claim 11 , wherein the first and second conductor structures comprise conductor pillars.
13. The method of claim 12 , wherein each of the first and second conductor structures comprises an end, the method comprising placing a solder structure on each of the ends.
14. A method of assembling a semiconductor chip device, comprising:
stacking a first semiconductor chip with a second semiconductor chip, the first semiconductor chip including a first edge, the second semiconductor chip including a side and first and second conductor structures projecting from the side; and
wherein the first semiconductor chip includes a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad toward the first edge and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.