Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
1. A method of manufacturing a stacked system of microelectronic dies, the method comprising:
forming an interconnect through a first microelectronic die such that an electrical connection between an integrated circuit and first electrical component carried by the first die is disabled;
aligning a second microelectronic die with the interconnect, the second die carrying a second electrical component; and
electrically coupling the interconnect with the second electrical component of the second die.
2. The method of claim 1 wherein forming an interconnect includes forming a hole through the substrate that removes a conduction path between the integrated circuit and another circuit component carried by the first die.
3. The method of claim 1 wherein the first die includes a first metal layer and a second metal layer, and wherein forming an interconnect comprises forming a hole through the first die that removes one or more metal vias that electrically couple the first metal layer with the second metal layer.
4. The method of claim 1 wherein the first die includes a first metal layer and a second metal layer, and wherein forming an interconnect comprises forming a hole through the first die that removes conductive portions of the first metal layer and/or the second metal layer.
5. The method of claim 1 wherein the second electrical component of the second die comprises an electrostatic discharge device.
6. A method of manufacturing a microelectronic workpiece, the method comprising:
forming a hole in a microelectronic substrate that carries a first circuit and a second circuit electrically connected to each other via a conduction path in the substrate, the hole being formed through the conduction path to electrically disconnect the first circuit and the second circuit from each other; and
at least partially lining a surface of the hole with a dielectric layer.
7. The method of claim 6 wherein the substrate includes a metal pad that is electrically coupled to the first circuit and the second circuit, and the forming of the hole in the substrate electrically isolates the second circuit from the metal pad after the hole is formed.
8. The method of claim 6 wherein forming a hole includes removing conductive material from the substrate associated with one or more metal vias of the substrate and/or one or more metal layers of the substrate.
9. The method of claim 6 , further comprising at least partially filling the hole with a metal, wherein the metal is adjacent to the dielectric layer.
10. The method of claim 6 wherein the second circuit comprises an electrostatic discharge device.
11. A method of manufacturing a stacked system of microelectronic dies comprising:
disabling a first electrostatic discharge (ESD) device from first internal circuitry of a first microelectronic die;
attaching a second microelectronic die to the first die in a stacked arrangement, wherein the second die has second internal circuitry and a second ESD device electrically coupled to the second internal circuitry, and wherein attaching the second die to the first die electrically couples the second ESD device to the first internal circuitry such that second ESD device protects the first internal circuitry and the second internal circuitry from electrostatic energy.
12. The method of claim 11 wherein the first and second ESD devices are redundant such that disabling the first ESD device reduces overall capacitive loading and improves the signal integrity of the stacked first and second dies.
13. The method of claim 12 wherein disabling the first ESD device comprises forming a hole in the first die that severs an electrical connection to the first ESD device.
14. The method of claim 13 , further comprising locating the hole at a bond pad and forming a conductive through-substrate interconnect in the hole, wherein the through-substrate interconnect is electrically connected to the second ESD device but is electrically isolated from the first ESD device.