Reconfigurable adder
In one embodiment, a reconfigurable adder has first and second five-bit non-reconfigurable adders and is selectively configurable to operate in a five-bit mode or a ten-bit mode. In five-bit mode, the first non-reconfigurable adder adds first and second messages to generate a first sum, and the second non-reconfigurable adder adds third and fourth messages to generate a second sum. In ten-bit mode, the first non-reconfigurable adder adds a first half of a first ten-bit message and a first half of a second ten-bit message to generate a first partial sum and a carry-over bit. The second non-reconfigurable adder adds a second half of the first ten-bit message, a second half of the second ten-bit message, and the carry-over bit to generate a second partial sum. A ten-bit sum is then generated by combining the first and second partial sums.
1. A node unit of a reconfigurable error-correction decoder comprising a reconfigurable adder, wherein:
the reconfigurable adder is adapted to receive a first set of bits and a second set of bits;
the reconfigurable adder comprises:
a first non-reconfigurable adder adapted to add (i) a first operand comprising a first subset of the first set of bits and (ii) a second operand comprising a first subset of the second set of bits to generate a first sum;
logic circuitry adapted to receive (i) a mode control signal and (ii) a most significant bit of the first sum and generate an intermediate value; and
a second non-reconfigurable adder adapted to add (i) a third operand comprising a second subset of the first set of bits, (ii) a fourth operand comprising a second subset of the second set of bits, and (iii) the intermediate value to generate a second sum;
the reconfigurable adder is selectively configurable to operate in a first operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a first number of bits; and
the reconfigurable adder is selectively configurable to operate in a second operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a second number of bits different from the first number of bits.
2. The node unit of claim 1 , wherein:
in the first operating mode:
the first, second, third, and fourth operands correspond to first, second, third, and fourth multi-bit values, respectively;
the first sum is a sum of the first and second multi-bit values;
the second sum is a sum of the third and fourth multi-bit values; and
the intermediate value is zero; and
in the second operating mode:
the first and third operands correspond to a first multi-bit value;
the second and fourth operands correspond to a second multi-bit value;
the first sum corresponds to least significant bits of a sum of the first and second multi-bit values;
the second sum corresponds to most significant bits of the sum of the first and second multi-bit values; and
the intermediate value is the most significant bit of the first sum.
3. The node unit of claim 1 , wherein the logic circuitry comprises an AND gate adapted to implement logical conjunction, based on a mode control signal and the most significant bit of the first sum, to generate the intermediate value as a carry-over bit.
4. The node unit of claim 1 , wherein:
in the first operating mode, the error-correction decoder is configured to process messages having the first number of bits; and
in the second operating mode, the error-correction decoder is configured to process messages having the second number of bits.
5. The node unit of claim 1 , wherein:
in the first operating mode, the node unit combines messages having the first number of bits; and
in the second operating mode, the node unit combines messages having the second number of bits.
6. The node unit of claim 1 , wherein the node unit is implemented in an integrated circuit.
7. The node unit of claim 1 , wherein the reconfigurable adder comprises hardware that is used in both the first and second operating modes.
8. The node unit of claim 7 , wherein the reconfigurable adder comprises hardware that is needed in the second operating mode but not the first operating mode.
9. The node unit of claim 1 , wherein the reconfigurable error-correction decoder is a low-density parity-check decoder.
10. The apparatus node unit of claim 9 , wherein the node unit is a variable-node unit.
11. The node unit of claim 1 , wherein:
the second number of bits is an integer multiple M of the first number of bits; and
in the first operating mode, the reconfigurable adder is adapted to add multi-bit values concurrently in M times as many pairs of multi-bit values as in the second operating mode.
12. The node unit of claim 11 , wherein M=2.
13. The node unit of claim 1 , wherein each multi-bit value is a message comprising a hard-decision bit and at least one confidence value bit.
14. An error-correction decoder comprising a reconfigurable adder, wherein:
the reconfigurable adder is selectively configurable to operate in a first operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a first number of bits; and
the reconfigurable adder is selectively configurable to operate in a second operating mode to add multi-bit values in a pair of multi-bit values, in which each multi-bit value has a second number of bits different from the first number of bits.
15. The error-correction decoder of claim 14 , wherein:
in the first operating mode, the error-correction decoder is configured to process messages having the first number of bits; and
in the second operating mode, the error-correction decoder is configured to process messages having the second number of bits.
16. The error-correction decoder of claim 14 comprising a node unit, wherein:
the node unit comprises the reconfigurable adder;
in the first operating mode, the node unit combines messages having the first number of bits; and
in the second operating mode, the node unit combines messages having the second number of bits.
17. The error-correction decoder of claim 14 , wherein the error-correction decoder is a low-density parity-check decoder.
18. The error-correction decoder of claim 14 , wherein the error-correction decoder is implemented in an integrated circuit.
19. The error-correction decoder of claim 14 , wherein:
the second number of bits is an integer multiple M of the first number of bits; and
in the first operating mode, the reconfigurable adder is adapted to add multi-bit values concurrently in M times as many pairs of multi-bit values as in the second operating mode.
20. The error-correction decoder of claim 19 , wherein M=2.