Semiconductor device
Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.
1. A semiconductor device comprising:
a semiconductor layer; and
first and second striped-patterned trenches formed in the semiconductor layer, the first and second striped-patterned trenches extending in a first direction in parallel with each other,
wherein each of the first and second striped-patterned trenches comprises:
a gate electrode housed in the striped-patterned trench with a gate insulating film intervening between the gate electrode and the semiconductor layer, a top face of the gate electrode being lower than a top face of the semiconductor layer; and
a buried insulating inter layer covering the gate electrode and housed in the striped-patterned trench,
wherein the semiconductor layer comprises:
a drain region of a first conductive type, each bottom part of the first and second striped-patterned trenches being formed in an upper part of the drain region;
a base region of a second conductive type formed on the drain region and between the first and second striped-patterned trenches, a bottom face of the base region having a downwardly curved profile; and
a source region of the first conductive type formed on the base region and between the first and second striped-patterned trenches, the source region having a substantially uniform thickness in a second direction from the first striped-patterned trench to the second striped-patterned trench, and
wherein a thickness of the base region at a center between the first and second striped-patterned trenches is thicker than that of each edge portion of the base region adjacent to the first and second striped-patterned trenches.
2. The semiconductor device of claim 1 , wherein the semiconductor layer further comprises:
a back gate region of the second conductive type formed in the base region and between the first and second striped-patterned trenches so that the back gate region is adjacent to the source region in the first direction, an impurity concentration of the back gate region being higher than that of the base region.
3. The semiconductor device of claim 2 , wherein a top face of the buried insulating interlayer is lower than the top face of the semiconductor layer which includes a top face of the source region and top face of the back gate region.
4. The semiconductor device of claim 3 , further comprising:
a source electrode formed on the top face of the buried insulating interlayer, the top face of the source region and the top face of the back gate region; and
a drain electrode formed on a back face of the semiconductor layer.
5. The semiconductor device of claim 4 , wherein the drain region comprises a lower layer and an upper layer, an impurity concentration of the lower layer being higher than that of the upper layer, and the back face of the semiconductor layer on which the drain electrode is formed corresponds to a back face of the lower layer.
6. The semiconductor device of claim 1 , wherein the bottom face of the base region interfaces with the drain region.
7. The semiconductor device of claim 1 , wherein the source region has a thickness in the first direction at edge portions of the source region adjacent to the first and second striped-patterned trenches greater than a thickness of the source region between the edge portions of the source region.