Display device and semiconductor device
View Patent ↗An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
1. A semiconductor device comprising:
a substrate;
a pixel comprising a thin film transistor over the substrate, the thin film transistor comprising:
a first channel formation region;
a second channel formation region; and
an impurity region between the first channel formation region and the second channel formation region;
an insulating layer over the thin film transistor;
a stacked layer over the insulating layer, the stacked layer comprising a first inorganic insulating film, a stress relaxation film and a second inorganic insulating film; and
a power supply line over the insulating layer,
wherein at least a part of the insulating layer is in contact with at least a part of the thin film transistor,
wherein the insulating layer includes an organic material, and
wherein the power supply line overlaps with the first channel formation region and the second channel formation region.
2. The semiconductor device according to claim 1 ,
wherein a channel width of the first channel formation region is longer than a channel length of the first channel formation region, and
wherein a channel width of the second channel formation region is longer than a channel length of the second channel formation region.
3. The semiconductor device according to claim 1 , wherein the first channel formation region and the second channel formation region are at least one of an amorphous semiconductor and a polycrystalline semiconductor.
4. The semiconductor device according to claim 1 , further comprising pixel electrodes adjacent to each other over the substrate, wherein at least a part of the power supply line is located between the pixel electrodes.
5. The semiconductor device according to claim 1 ,
wherein a channel width direction of the first channel formation region is perpendicular to a channel length direction of the first channel formation region in which current flows through the first channel formation region and is parallel to a longitudinal direction of a region of the power supply line which overlapping with the first channel formation region, and
wherein a channel width direction of the second channel formation region is perpendicular to a channel length direction of the second channel formation region in which current flows through the second channel formation region and is parallel to a longitudinal direction of a region of the power supply line which overlapping with the second channel formation region.
6. The semiconductor device according to claim 4 ,
wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the pixel electrodes, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the power supply line.
7. A semiconductor device comprising:
a substrate;
a first pixel and a second pixel adjacent to the first pixel, the first pixel and the second pixel over the substrate each comprising:
a first pixel electrode;
a light emitting layer over the first pixel electrode; and
a second pixel electrode over the light emitting layer;
a thin film transistor over the substrate;
an insulating layer over the thin film transistor; and
a power supply line over the insulating layer and between the first pixel electrodes of the first pixel and the second pixel; and
wherein the power supply line overlaps with a channel formation region of the thin film transistor, and
wherein the light emitting layer and the second pixel electrode of the first pixel overlap with the channel formation region of the thin film transistor.
8. The semiconductor device according to claim 7 , wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
9. The semiconductor device according to claim 7 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
10. The semiconductor device according to claim 7 ,
wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the first pixel electrodes of the first pixel and the second pixel, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the power supply line.
11. The semiconductor device according to claim 7 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the power supply line which overlapping with the channel formation region.
12. A semiconductor device comprising:
a substrate;
elements adjacent to each other over the substrate;
a pixel comprising a thin film transistor over the substrate, the thin film transistor comprising:
a first channel formation region;
a second channel formation region; and
an impurity region between the first channel formation region and the second channel formation region;
an insulating layer over the thin film transistor;
a wiring over the insulating layer and between the elements; and
a gate wiring arranges so as to cross the wiring,
wherein at least a part of the insulating layer is in contact with at least a part of the thin film transistor,
wherein the insulating layer includes an organic material, and
wherein the wiring overlaps with the first channel formation region and the second channel formation region.
13. The semiconductor device according to claim 12 ,
wherein a channel width of the first channel formation region is longer than a channel length of the first channel formation region, and
wherein a channel width of the second channel formation region is longer than a channel length of the second channel formation region.
14. The semiconductor device according to claim 12 , wherein the first channel formation region and the second channel formation region are at least one of an amorphous semiconductor and a polycrystalline semiconductor.
15. The semiconductor device according to claim 12 ,
wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the elements, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
16. The semiconductor device according to claim 12 ,
wherein a channel width direction of the first channel formation region is perpendicular to a channel length direction of the first channel formation region in which current flows through the first channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the first channel formation region, and
wherein a channel width direction of the second channel formation region is perpendicular to a channel length direction of the second channel formation region in which current flows through the second channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the second channel formation region.
17. The semiconductor device according to claim 12 , wherein each of the elements is a light-emitting element, an organic memory, a photo diode or a piezoelectric element.