Low-noise amplifier with gain enhancement

1. A low-noise amplifier (“LNA”), comprising:

a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node;

a first inductive gate network coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage, the first inductive gate network having a non-zero inductive input impedance and including at least one passive circuit element;

a second cascode gain stage coupled to the first cascode gain stage; and

a first variable gain network coupled to a gate of a first transistor of the second cascode gain stage that is coupled to a second transistor of the second cascode gain stage, the first variable gain network including

an inductor for boosting a gain of the second cascode gain stage,

a capacitor coupled to the inductor for blocking a direct current (“DC”) voltage, and

a third transistor coupled to the inductor and to the capacitor, the third transistor configured to selectively couple the inductor to the second cascode stage in response to a control signal received at a gate of the third transistor to increase an inductance at the gate of the first transistor of the first variable gain network.

2. The LNA of claim 1 , wherein the inductive gate network includes one of a capacitor or a varactor for filtering a direct current (“DC”) voltage.

3. The LNA of claim 1 , wherein the at least one passive circuit element includes an inductor or an inductive transmission line.

4. The LNA of claim 3 , wherein the passive transmission line includes one of a microstrip or a coplanar waveguide.

5. The LNA of claim 1 , further comprising:

an input matching network coupled between the input node and the first cascode gain stage.

6. The LNA of claim 1 , further comprising:

a first inter-stage matching network coupled to an output of the first cascode gain stage and to an input of the second cascode gain stage.

7. The LNA of claim 1 , wherein the first CMOS transistor has a source coupled to ground and a drain coupled to a source of the second CMOS transistor, and the second CMOS transistor has a drain coupled to the output node.

8. A low-noise amplifier (“LNA”), comprising:

a plurality of cascode gain stages for increasing an amplitude of a radio frequency (“RF”) input signal, each of the cascode gain stages including

a first transistor having a source coupled to ground and a gate coupled an input node of the respective gain stage for receiving an RF input signal to the respective gain stage, and

a second transistor having a source coupled to a drain of the first transistor and a drain coupled to an output node of the respective gain stage;

at least one inductive gate network having a non-zero input impedance and including at least one passive circuit element coupled to a gate of the second transistor in at least one of the plurality of cascode gain stages; and

at least one variable gain network coupled to a gate of the second transistor in at least one of the plurality of cascode gain stages, the at least one variable gain network including

an inductor for boosting a gain of the cascode gain stage to which the at least one variable gain network is coupled,

a capacitor coupled to the inductor for blocking a direct current (“DC”) voltage, and

a third transistor coupled to the inductor and to the capacitor, the third transistor configured to selectively couple the inductor to the gate of the second transistor of the cascode gain stage to which the at least one variable gain network is coupled in response to a control signal received at a gate of the third transistor to increase an inductance at the gate of the second transistor of the cascode gain stage to which the at least one variable gain network is coupled.

9. The LNA of claim 8 , wherein the at least one passive circuit element includes one of an inductor or an inductive transmission line.

10. The LNA of claim 9 , wherein the inductive transmission line includes one of a microstrip or a coplanar waveguide.

11. The LNA of claim 8 , wherein the inductive gate network includes one of a capacitor or a varactor for removing a direct current (“DC”) bias voltage from the inductive gate network.

12. A method, comprising:

receiving a first radio frequency (“RF”) signal at an input node for a first cascode gain stage, a first inductive gate network having a non-zero input impedance and at least one passive circuit device is coupled to a gate of a first common gate transistor of the first cascode gain stage;

increasing an amplitude of the first RF signal at the first cascode gain stage to produce a second RF signal;

outputting the second RF signal having an amplitude greater than an amplitude of the first RF signal to an output node of the first cascode gain stage coupled to the first common gate transistor

receiving the second RF signal at an input node for a second cascode gain stage;

selectively coupling a variable gain network to a gate of a second common gate transistor of the second cascode gain stage in response to receiving a control signal at a gate of a third transistor to increase an impedance at the gate of the second transistor thereby further increasing the amplitude of the second RF signal to produce a third RF signal.

13. The method of claim 12 , wherein the passive circuit device of the first inductive gate network includes at least one of an inductor, a capacitor, a varactor, or an inductive transmission line.

14. The method of claim 13 , wherein the inductive transmission line includes at least one of a microstrip or a coplanar waveguide.

15. The method of claim 12 , further comprising:

receiving the third RF signal at an input node for a third cascode gain stage, the third cascode gain stage having a second inductive gate network having a non-zero input impedance coupled to a third common gate transistor in the second cascode gain stage;

increasing an amplitude of the third RF signal at the third cascode gain stage to produce a fourth RF signal; and

outputting the fourth RF signal having an amplitude greater than the amplitude of the third RF signal to an output node for the third gain stage coupled to the third common gate transistor.

16. The method of claim 12 , further comprising:

receiving a third fourth RF signal at an input node for a third cascode gain stage;

selectively coupling a variable gain network to a gate of a third common gate transistor of the third cascode gain stage to increase an amplitude of the third RF signal and produce the first RF signal; and

outputting the first RF signal having an amplitude greater than the amplitude of the third RF signal to the input node for the first input gain stage.

17. The method of claim 16 , wherein the variable gain network is selectively coupled to the gate of the second common gate transistor through a switch.

18. A method, comprising

receiving a first radio frequency (“RF”) signal at an input node for a first cascode gain stage,

selectively coupling a variable gain network to a gate of a first common gate transistor of the first cascode gain stage in response to receiving a control signal at a gate of a transistor to increase an impedance at the gate of the first common gate transistor thereby increasing the amplitude of the first RF signal to produce a second RF signal;

increasing an amplitude of the second RF signal at a second cascode gain stage to produce a third RF signal, the second cascode gain stage including a second common gate transistor to which a first inductive gate network is coupled, the first inductive gate network having a non-zero input impedance and at least one passive circuit device coupled to the gate of the second common gate transistor of the second cascode gain stage; and

outputting the third RF signal having an amplitude greater than an amplitude of the second RF signal to an output node of the second cascode gain stage coupled to the second common gate transistor.

19. The method of claim 18 , further comprising:

receiving the third RF signal at an input node for a third cascode gain stage, the third cascode gain stage having a second inductive gate network having a non-zero input impedance coupled to a third common gate transistor in the second cascode gain stage;

increasing an amplitude of the third RF signal at the third cascode gain stage to produce a fourth RF signal; and

outputting the fourth RF signal having an amplitude greater than the amplitude of the third RF signal to an output node for the third gain stage coupled to the third common gate transistor.