Through-silicon via structure and a process for forming the same
View Patent ↗A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.
1. A device, comprising:
a semiconductor substrate having a front surface and a back surface and including an integrated circuit (IC) component formed on the front surface;
an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;
a contact plug formed in the ILD layer and electrically coupled to the IC component; and
a via structure formed in the ILD layer and extending through the semiconductor substrate, wherein the via structure comprises a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer sandwiched between at least a portion of the metal layer and at least a portion of the metal seed layer.
2. The device of claim 1 , wherein the metal silicide layer comprises copper.
3. The device of claim 1 , wherein the metal layer comprises copper, and the metal seed layer comprises copper.
4. The device of claim 1 , wherein the barrier layer comprises TaN, Ta, TiN, Ti or combinations thereof.
5. The device of claim 1 , wherein the via structure comprises a passivation layer surrounding the barrier layer.
6. The device of claim 5 , wherein the passivation layer comprises silicon oxide.
7. The device of claim 1 , wherein the via structure includes an end exposed on the back surface of the semiconductor substrate.
8. The device of claim 1 , further comprising a semiconductor component stacked on the back surface of the semiconductor substrate and electrically connected to the via structure.
9. A semiconductor device, comprising:
a semiconductor substrate having a front surface and a back surface and including an integrated circuit (IC) component formed on the front surface;
an interlayer dielectric (ILD) layer formed overlying the front surface of the semiconductor substrate;
a contact plug formed in the ILD layer and electrically coupled to the IC component; and
a via structure formed in the ILD layer and extending through the semiconductor substrate;
wherein the via structure comprises a copper layer, a copper seed layer surrounding the copper layer, a barrier layer surrounding the copper seed layer, and a copper silicide layer sandwiched between at least a portion of the copper layer and at least a portion of the copper seed layer; and
wherein the via structure includes an end exposed on the back surface of the semiconductor substrate.
10. The semiconductor device of claim 9 , wherein the barrier layer comprises TaN, Ta, TiN, Ti or combinations thereof.
11. The semiconductor device of claim 9 , further comprising a passivation layer surrounding the barrier layer.
12. The semiconductor device of claim 11 , wherein the passivation layer comprises silicon oxide.
13. The semiconductor device of claim 9 , further comprising
a backside dielectric layer formed overlying the back surface of the semiconductor substrate; and
an external contact formed on the backside dielectric layer.
14. The semiconductor device of claim 13 , wherein the external contact comprises solder bumps, copper-containing bumps or combinations thereof.