Circuit simulation method
A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.
1. A simulation method for a semiconductor circuit that comprises:
a semiconductor resistor;
a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and
a wiring line formed on the plurality of contacts,
the simulation method comprising:
defining a ratio of a parasitic-resistance of the semiconductor resistor between two of the plurality of contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and
modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net comprising the terminal region of the semiconductor resistor and the plurality of contacts.
2. The simulation method according to claim 1 , wherein the constant k is defined by
k
=
ρ
spol
×
pctl
×
nctw
rct
×
w
,
where
ρspol is a sheet resistance value of the semiconductor resistor,
pctl is a pitch of the plurality of contacts in the longitudinal direction of the semiconductor resistor,
nctw is the number of contacts arranged in the width direction,
rct is a resistance value of one of the plurality of contacts, and
w is a width of the semiconductor resistor at the terminal region.
3. The simulation method according to claim 1 , wherein in the modeling, a three-term recurrence formula derived from a relationship of three currents that flow through three contacts neighboring each other in the longitudinal direction is used.
4. The simulation method according to claim 1 , wherein in the modeling, the parasitic-resistance of the wiring line positioned immediately above the terminal region is neglected.
5. The simulation method according to claim 1 , wherein a width of the semiconductor resistor is constant over the whole of the semiconductor resistor.
6. The simulation method according to claim 1 , wherein
the terminal region is formed at ends of the semiconductor resistor, and
the parasitic resistance net is modeled, in the modeling, as an equivalent resistance composed of a single resistance series-connected between a resistance of a main body of the wiring line and a resistance of a main body of the semiconductor resistor.
7. The simulation method according to claim 1 , wherein
the terminal region is formed at a center of the semiconductor resistor, and
in the modeling, the parasitic resistance net is modeled as an equivalent resistance comprising:
a first partial resistance, one end of which is connected to a resistance of a main body of the wiring line; and
two second partial resistances, one end of which is connected to the other end of the first partial resistance and the other end of which is connected to a main body of the semiconductor resistor formed at each side of the terminal region.