IP Library Granted Patent US 8,435,832
Granted Patent B2
US 8,435,832 · App. 13/406,824 · Granted May 7, 2013

Double self-aligned metal oxide TFT

Inventors: Chan-Long Shieh (Paradise Valley, AZ); Gang Yu (Santa Barbara, CA)
Assignee: CBRITE Inc.
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Quick Facts
Patent No.
US 8,435,832
App. No.
13/406,824
Granted
May 7, 2013
Kind
B2
Abstract

A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.

Claims (43)

1. A method of fabricating metal oxide TFTs on transparent substrates comprising the steps of:

providing a transparent substrate having a front surface and a rear surface;

positioning opaque gate metal on the front surface of the substrate to define a gate area for a TFT;

depositing a layer of transparent gate dielectric on the front surface of the substrate overlying the gate metal and a surrounding area and a layer of transparent metal oxide semiconductor material on the surface of the layer of transparent gate dielectric;

depositing a layer of passivation material on the layer of metal oxide semiconductor material;

exposing portions of the layer of passivation material from the rear surface of the substrate and removing exposed portions of the layer of passivation material to leave a passivation area defining a channel area for the TFT overlying the gate area;

depositing a seed layer of thin conductive material on the layer of metal oxide semiconductor material;

depositing a layer of positive working photo resist material on the seed layer;

exposing portions of the layer of positive working photo resist material from the rear surface of the substrate and removing exposed portions of the layer of positive working photo resist material to leave a portion of the positive working photo resist material overlying the channel area and leaving exposed areas of the seed layer defining source/drain areas for the TFT;

plating a relatively thick layer of conductive metal on the exposed areas of the seed layer; and

using the layer of conductive metal, removing the portion of the positive working photo resist material and the seed layer overlying the channel area.

2. A method as claimed in claim 1 wherein the step of plating the conductive metal includes plating one of Cu, Ni, Cr, and combinations thereof.

3. A method as claimed in claim 2 wherein the step of depositing the passivation layer includes depositing and processing a patternable material as the layer of passivation material.

4. A method as claimed in claim 1 wherein the step of depositing the seed layer of thin transparent conductive material includes depositing one of a transparent conductive metal oxide, a transparent layer of thin metal, and a transparent organic layer.

5. A method as claimed in claim 4 wherein the step of depositing the seed layer includes depositing one of Pt, Pd, and Au.

6. A method as claimed in claim 1 including a step of incorporating the metal oxide TFTs into one of electronic devices and circuits including thin film OLED and LCD circuits, thin film driving circuits, active matrix LED, OLED and LCD displays, imaging array devices and thin film readout devices.

7. A method of fabricating metal oxide TFTs on transparent substrates comprising the steps of:

providing a transparent substrate having a front surface and a rear surface;

positioning opaque gate metal on the front surface of the substrate to define a gate area for a TFT;

depositing a layer of transparent gate dielectric on the front surface of the substrate overlying the gate metal and a surrounding area and a layer of transparent metal oxide semiconductor material on the surface of the layer of transparent gate dielectric;

depositing a layer of passivation material on the layer of metal oxide semiconductor material;

exposing portions of the layer of passivation material from the rear surface of the substrate and removing exposed portions of the layer of passivation material to leave a passivation area defining a channel area for the TFT overlying the gate area and leaving exposed areas of the metal oxide semiconductor material defining source/drain areas for the TFT;

depositing a relatively thick layer of conductive metal material on the exposed areas of the layer of metal oxide semiconductor material; and

processing the layer of conductive metal material to provide thick metal source/drain contacts in communication with the metal oxide semiconductor material in the source/drain areas.

8. A method as claimed in claim 7 wherein the layer of passivation material is positive photoresist.

9. A method as claimed in claim 7 wherein the step of depositing a relatively thick layer of conductive metal material includes printing, dipping, or coating.

10. A method as claimed in claim 9 wherein the step of depositing a relatively thick layer of conductive metal material includes depositing a conductive paste.

11. A method as claimed in claim 10 wherein the step of depositing the layer of conductive paste includes depositing silver paste, carbon black paste, or carbon nanotube paste.

12. A method as claimed in claim 10 wherein the step of processing the layer of conductive metal material includes heating the conductive paste to remove solvents or organic groups.

13. A method as claimed in claim 7 including a step of incorporating the metal oxide TFTs into one of electronic devices and circuits including thin film OLED and LCD circuits, thin film driving circuits, active matrix LED, OLED and LCD displays, imaging array devices and thin film readout devices.

14. A method of fabricating metal oxide TFTs on transparent substrates comprising the steps of:

providing a transparent substrate having a front surface and a rear surface;

positioning opaque gate metal on the front surface of the substrate to define a gate area for a TFT;

depositing a layer of transparent gate dielectric on the front surface of the substrate overlying the gate metal and a surrounding area and a layer of transparent metal oxide semiconductor material on the surface of the layer of transparent gate dielectric overlying the gate metal and the surrounding area;

depositing a layer of passivation material on the layer of metal oxide semiconductor material overlying the gate metal and the surrounding area;

exposing portions of the layer of passivation material from the rear surface of the substrate and removing exposed portions of the layer of passivation material to leave a passivation area defining a channel area for the TFT overlying the gate area and source/drain areas for the TFT on either side of the channel area; and

selectively depositing a relatively thick layer of conductive metal material on the exposed areas of the layer of metal oxide semiconductor material.

15. A method as claimed in claim 14 wherein the step of selectively depositing the relatively thick layer of conductive metal material includes the steps of providing a seed layer of thin conductive material and plating a conductive metal on the seed layer.

16. A method as claimed in claim 14 wherein the step of selectively depositing the relatively thick layer of conductive metal material includes the steps of depositing a metal paste material on the exposed areas of the layer of metal oxide semiconductor material and processing the metal paste material to provide thick metal source/drain contacts in communication with the metal oxide semiconductor material in the source/drain areas.

17. A method as claimed in claim 14 including a step of incorporating the metal oxide TFTs into one of electronic devices and circuits including thin film OLED and LCD circuits, thin film driving circuits, active matrix LED, OLED and LCD displays, imaging array devices and thin film readout devices.

18. A method as claimed in claim 14 wherein the step of exposing portions of the layer of passivation material includes one of laser scanning and shaped light scanning.

19. A method as claimed in claim 18 wherein the step of exposing portions of the layer of passivation material uses laser scanning and includes tuning laser pulse time and duration to align with substrate dimension changes, thereby allowing the use of a thin organic flexible substrate.

20. A method as claimed in claim 14 wherein the steps of exposing portions of the layer of passivation material and selectively depositing a relatively thick layer of conductive metal material include forming buslines and other circuitry in the relatively thick layer of conductive metal material.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED ON REEL 048069 FRAME 0427. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Apr 13, 2020
From: FULL STRENGTH GROUP LIMITED
To: ABC SERVICES GROUP, INC., SOLELY IN ITS CAPACITY AS ASSIGNEE FOR THE BENEFIT OF CREDITORS OF CBRITE INC.; CBRITE INC.
Reel/Frame 052384/0832 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED AT REEL: 045653 FRAME: 0823. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 13, 2020
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 052377/0853 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED AT REEL: 045653 FRAME: 0983. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 13, 2020
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 052377/0913 →
CORRECTIVE ASSIGNMENT TO CORRECT THE LIST OF PROPERTIES SO THAT IT DOES NOT INCLUDE US PATENT NO. 8233212 PREVIOUSLY RECORDED ON REEL 049879 FRAME 0645. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded Apr 13, 2020
From: ABC SERVICES GROUP, INC.
To: FANTASY SHINE LIMITED
Reel/Frame 052384/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2019
From: ABC SERVICES GROUP, INC.
To: FANTASY SHINE LIMITED
Reel/Frame 049879/0645 →
RELEASE OF SECURITY INTEREST Recorded Jan 14, 2019
From: FULL STRENGTH GROUP LIMITED
To: ABC SERVICES GROUP, INC., SOLELY IN ITS CAPACITY AS ASSIGNEE FOR THE BENEFIT OF CREDITORS OF CBRITE INC.; CBRITE INC.
Reel/Frame 048069/0427 →
SECURITY INTEREST Recorded Mar 20, 2018
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 045653/0823 →
SECURITY INTEREST Recorded Mar 20, 2018
From: CBRITE INC.
To: FULL STRENGTH GROUP LIMITED
Reel/Frame 045653/0983 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2013
From: SHIEH, CHAN-LONG; YU, GANG
To: CBRITE INC.
Reel/Frame 030131/0182 →
Continuity (2)
Continuation In Part 13116292 · May 26, 2011
Related Publication 20120302003A1 · Nov 29, 2012