IP Library Granted Patent US 8,441,064
Granted Patent B2
US 8,441,064 · App. 13/207,961 · Granted May 14, 2013

Scalable interpoly dielectric stacks with improved immunity to program saturation

Inventors: Bogdan Govoreanu (Hulshout, BE); Stefan De Gendt (Wijnegem, BE); Sven Van Elshocht (Heverlee, BE); Tom Schram (Rixensart, BE)
Assignee: IMEC
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Quick Facts
Patent No.
US 8,441,064
App. No.
13/207,961
Granted
May 14, 2013
Kind
B2
Abstract

A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Claims (26)

1. A non-volatile memory device comprising:

a substrate comprising a channel in between two doped regions;

a first dielectric on top of said channel, said first dielectric having predetermined properties for functioning as a tunnel dielectric;

a charge storage layer on top of said tunnel dielectric, said charge storage layer having predetermined properties for enabling storage of charge in said layer and comprising an upper layer containing silicon dioxide;

a second dielectric, comprising a layer in a siliconoxide consuming material on top of said upper layer of the charge storage layer whereby said siliconoxide consuming material having consumed at least part of said upper layer, on top of said charge storage layer, said second dielectric having predetermined properties for minimizing charge currents through the second dielectric; and

a control gate on top of said second dielectric.

2. The non-volatile memory device according to claim 1 , wherein the layer of siliconoxide consuming material forms substantially the whole of the second dielectric.

3. The non-volatile memory device according to claim 1 , wherein the second dielectric comprises a layer of low-k material on top of the layer of siliconoxide consuming material.

4. The non-volatile memory device according to claim 1 , wherein the second dielectric comprises another layer in the siliconoxide consuming material on top of the layer of low-k material.

5. The non-volatile memory device according to claim 1 , wherein the control gate is formed in a material having a high work function.

6. The non-volatile memory device according to claim 5 , wherein the work function is about 4 eV or higher.

7. The non-volatile memory device according to claim 1 , wherein the siliconoxide consuming material comprises a rare earth material.

8. The non-volatile memory device according to claim 7 , wherein the siliconoxide consuming material is dysprosium scandate, DyScO.

9. A non-volatile memory device comprising:

a substrate comprising a channel in between two doped regions;

a first dielectric on top of said channel, said first dielectric having predetermined properties for functioning as a tunnel dielectric;

a charge storage layer on top of said tunnel dielectric, said charge storage layer having predetermined properties for enabling storage of charge in said layer;

a second dielectric, comprising a layer in a siliconoxide consuming material on top of said charge storage layer, said second dielectric having predetermined properties for minimizing charge currents through the second dielectric; and

a control gate on top of said second dielectric.

10. The non-volatile memory device according to claim 9 , wherein the layer of siliconoxide consuming material forms substantially the whole of the second dielectric.

11. The non-volatile memory device according to claim 9 , wherein the second dielectric comprises a layer of low-k material on top of the layer of siliconoxide consuming material.

12. The non-volatile memory device according to claim 9 , wherein the second dielectric comprises another layer in the siliconoxide consuming material on top of the layer of low-k material.

13. The non-volatile memory device according to claim 9 , wherein the control gate is formed in a material having a high work function.

14. The non-volatile memory device according to claim 13 , wherein the work function is about 4 eV or higher.

15. The non-volatile memory device according to claim 9 , wherein the siliconoxide consuming material comprises a rare earth material.

16. The non-volatile memory device according to claim 15 , wherein the siliconoxide consuming material is dysprosium scandate, DyScO.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2011
From: GOVOREANU, BOGDAN; DE GENDT, STEFAN; VAN ELSHOCHT, SVEN; SCHRAM, TOM
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
Reel/Frame 026770/0517 →
CHANGE OF NAME Recorded Aug 18, 2011
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
To: IMEC
Reel/Frame 026770/0675 →
Priority Claims (1)
EP 08153100 · Mar 20, 2008 · regional
Continuity (3)
Division 12338015 · Dec 18, 2008
Provisional Application 61016862 · Dec 27, 2007
Related Publication 20110291179A1 · Dec 1, 2011