Gate structures

1. An apparatus comprising:

a substrate;

a first device that includes a first projection and a first gate structure, the first projection extending upwardly from the substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region, the first structure including:

a high-k first dielectric material over the first channel region;

an opening over the first dielectric material and the first channel region; and

a conformal, pure metal with a low resistivity disposed in the opening; and

a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region, the second structure including:

a second dielectric material over the second channel region; and

a silicide disposed over the second dielectric material and second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

2. An apparatus according to claim 1 , wherein the opening has a high aspect ratio and the metal fills the opening.

3. An apparatus according to claim 1 , wherein the second gate structure includes a doped polysilicon layer disposed between the second dielectric material and the silicide.

4. An apparatus according to claim 1 , wherein the first device is a p-type metal oxide semiconductor (PMOS) device and the second device is an n-type metal oxide semiconductor (NMOS) device.

5. An apparatus according to claim 4 , wherein the pure metal is one of cobalt (Co), nickel (Ni), and platinum (Pt).

6. An apparatus according to claim 4 ,

wherein the first device is a long channel device;

wherein the pure metal fills a portion of the opening; and

wherein the first gate structure includes a fill metal in a remaining portion of the opening.

7. A semiconductor device, comprising:

a semiconductor substrate;

a first fin-like field effect transistor (FinFET) disposed over the semiconductor substrate and including a first gate structure adjacent a first channel region, the first gate structure including a high-k dielectric layer and a silicided gate electrode; and

a short-channel second FinFET disposed adjacent the first FinFET and over the semiconductor substrate, the short-channel second FinFET including a second gate structure adjacent a second channel region, and the second gate structure including the high-k dielectric layer and a pure metal gate electrode.

8. A semiconductor device according to claim 7 , wherein the silicided gate electrode includes a metal that is the same metal that forms the pure metal gate electrode.

9. A semiconductor device according to claim 7 , wherein the pure metal gate electrode is disposed within an opening having a high-aspect ratio.

10. A semiconductor device according to claim 7 , wherein the first gate structure includes a doped polysilicon layer disposed between the high-k dielectric layer and the silicided gate electrode.

11. A semiconductor device according to claim 7 , wherein the pure metal gate electrode is formed of one of cobalt (Co), nickel (Ni), and platinum (Pt).

12. A semiconductor device according to claim 7 , wherein the first gate structure includes a barrier layer disposed between the high-k dielectric layer and the silicided gate electrode.

13. A semiconductor device according to claim 12 , wherein the barrier layer includes one of titanium nitride (TiN), tantalum nitride (TaN), and a metal carbide.