Current steering DAC with switched cascode output current source/sink
A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.
1. A current-steering digital-to-analog converter (DAC) comprising:
a plurality of current cells, each current cell comprising
a dual bias switched cascode output current source having a plurality of control terminals configured to define bias inputs, and
a pair of complementary bias switching devices coupled between a reference voltage and the bias inputs of said dual bias switched cascode output current source,
each complementary bias switching device including a control input configured to receive a respective complementary switching signal.
2. The current-steering DAC of claim 1 wherein each complementary bias switching device comprises a multiplexer.
3. The current-steering DAC of claim 1 wherein each complementary bias switching device comprises a transmission gate.
4. The current-steering DAC of claim 1 wherein each complementary bias switching device comprises a charge balancing device.
5. The current-steering DAC of claim 4 wherein said charge balancing device comprises an electronic switch, and a charge storage device coupled thereto.
6. The current-steering DAC of claim 5 wherein said charge storage device comprises a capacitor.
7. An integrated circuit (IC) comprising:
a plurality of current cells configured to define a current-steering digital-to-analog converter (DAC), each current cell comprising
a dual bias switched cascode output current source having a plurality of control terminals configured to define bias inputs, and
a pair of complementary bias switching devices coupled between a reference voltage and the bias inputs of said dual bias switched cascode output current source,
each complementary bias switching device including a control input configured to receive a respective complementary switching signal.
8. The IC of claim 7 wherein each complementary bias switching device comprises a transmission gate.
9. The IC of claim 7 wherein each complementary bias switching device comprises a multiplexer.
10. The IC of claim 7 wherein each complementary bias switching device comprises a charge balancing device.
11. The IC of claim 10 wherein said charge balancing device comprises an electronic switch, and a charge storage device coupled thereto.
12. The IC of claim 11 wherein said charge storage device comprises a capacitor.
13. A current cell for a current-steering digital-to-analog converter (DAC), the current cell comprising:
a dual bias switched cascode output current source having a plurality of control terminals configured to define bias inputs; and
a pair of complementary bias switching devices coupled between a reference voltage and the bias inputs of said dual bias switched cascode output current source;
each complementary bias switching device including a control input configured to receive a respective complementary switching signal.
14. The current cell of claim 13 wherein each complementary bias switching device comprises a multiplexer.
15. The current cell of claim 13 wherein each complementary bias switching device comprises a transmission gate.
16. The current cell of claim 13 wherein each complementary bias switching device comprises a charge balancing device.
17. The current cell of claim 16 wherein said charge balancing device comprises an electronic switch, and a charge storage device coupled thereto.
18. The current cell of claim 17 wherein said charge storage device comprises a capacitor.
19. A method of operating a digital-to-analog converter (DAC) using a plurality of current-steering cascode current sources, the method comprising:
connecting each current-steering cascode current source into a dual output cascode source having a pair of control terminals defining cascode bias inputs; and
selectively coupling a cascode bias voltage to one of the cascode bias inputs of the dual output cascode source while disabling a bias to the other cascode bias input using a plurality of complementary bias switching devices coupled between a reference voltage and the cascode bias inputs.
20. The method of claim 19 further comprising charge balancing at a cascode bias node during switching of the cascode bias voltage from one cascode bias input to another.
21. The method of claim 20 wherein the charge balancing is provided at the cascode bias node by coupling a compensating charge storage element to the bias node.
22. A method of making a current-steering digital-to-analog converter (DAC), the method comprising:
coupling a plurality of current cells to each other, each current cell comprising
a dual bias switched cascode output current source having a plurality of control terminals defining bias inputs, and
a pair of complementary bias switching devices coupled between a reference voltage and the bias inputs of the dual bias switched cascode output current source,
each complementary bias switching device including a control input configured to receive a respective complementary switching signal.
23. The method of claim 22 wherein each complementary bias switching device comprises a multiplexer.
24. The method of claim 22 wherein each complementary bias switching device comprises a transmission gate.
25. The method of claim 22 wherein each complementary bias switching device comprises a charge balancing device.
26. The method of claim 25 wherein the charge balancing device comprises an electronic switch, and a charge storage device coupled thereto.
27. The method of claim 26 wherein the charge storage device comprises a capacitor.