Circuit and method for generating pumping voltage in semiconductor memory apparatus and semiconductor memory apparatus using the same
A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.
1. A circuit for generating a pumping voltage, comprising:
a voltage applying unit configured to supply an external voltage to a first node in response to a first transmission signal;
a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal; and
a first outputting unit comprising a plurality of connection units, wherein
the plurality of connection units are connected in parallel to interconnect the first node with a second node.
2. The circuit according to claim 1 , wherein the plurality of connection units are driven to interconnect the first node and the second node when a second transmission signal is enabled.
3. The circuit according to claim 1 , further comprising a control signal generation block configured to generate a plurality of control signals obtained by level-shifting a voltage level of a plurality of test signals to a plurality of driving voltage levels respectively, wherein the plurality of control signals are operable to enable the plurality of connection units.
4. The circuit according to claim 3 , wherein an enabling voltage level of a second transmission signal is higher than an enabling voltage level of the first transmission signal.
5. The circuit according to claim 4 , wherein a first driving voltage level of the plurality of driving voltage levels is substantially the same as the enabling voltage level of the second transmission signal.
6. The circuit according to claim 4 , wherein the control signal generation block is configured such that a voltage level of a first control signal is substantially the same as the enabling voltage level of the second transmission signal.
7. The circuit according to claim 6 , wherein the control signal generation block includes a level shifter that level-shifts the test signal to the first driving voltage level and generates the first control signal.
8. The circuit according to claim 3 , wherein each of the plurality of connection units includes:
a selection part configured to output a voltage of the first node in response to one of the plurality of control signals; and
a transmission part configured to output an output of the selection part to the second node in response to a second transmission signal.
9. The circuit according to claim 8 , wherein the selection part and the transmission part include a plurality of transistors.
10. The circuit according to claim 3 , further comprising a second outputting unit connected with the second node which corresponds to an output of the first outputting unit, wherein the second outputting unit includes a second plurality of connection units.
11. The circuit according to claim 10 , wherein each of the plurality of second connection units is configured to interconnect the second node and a third node.
12. The circuit according to claim 11 , wherein the plurality of second connection units are driven to interconnect the second node and the third node when a third transmission signal is enabled.
13. The circuit according to claim 12 , wherein a second driving voltage level of the plurality of driving voltage levels is higher than a first driving voltage level of the plurality of driving voltage levels, and is substantially the same as an enabling voltage level of the third transmission signal.
14. The circuit according to claim 11 , wherein each of the second plurality of connection units includes:
a selection part configured to output a voltage of the second node in response to a second control signal; and
a transmission part configured to output an output of the selection part to the third node in response to the third transmission signal.
15. The circuit according to claim 14 , wherein the selection part and the transmission part include a plurality of transistors.
16. The circuit according to claim 1 , further comprising a second charge pump configured to raise a voltage level of the second node by a second predetermined level in response to an inverted oscillator signal.