Disparate clock domain synchronization
Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.
1. An integrated circuit comprising:
a core circuit to operate in a first clock domain; and
an input/output (I/O) circuit to operate in a second clock domain different than the first clock domain, the I/O circuit to include a sequential circuit to send data to and receive data from the core circuit, and a control circuit to control operation of the sequential circuit via a timing offset signal; the core circuit to further
transmit a test data sequence to the I/O circuit,
receive a delayed transmission of the test data sequence from the sequential circuit of I/O circuit,
compare the timing offset of the delayed transmission with a stored timing offset determined during a link training between the core and I/O circuit, and
adjust the timing offset signal of the control circuit included in the I/O circuit if the timing offset of the delayed transmission and the stored timing offset differ;
wherein the first clock domain comprises at least one of a different phase or a different frequency than the second clock domain.
2. The integrated circuit of claim 1 , the core circuit to transmit the test data sequence to the I/O circuit in response to the I/O circuit exiting a low power state.
3. The integrated circuit of claim 1 , wherein the sequential circuit of the I/O circuit comprises a first in first out (FIFO) circuit.
4. The integrated circuit of claim 1 , the core circuit to further include a delay circuit including the stored timing offset, wherein comparing the timing offset of the delayed transmission with the stored timing offset determined during the link training between the core and I/O circuit comprises:
processing the test data via the delay circuit to generate a second delayed transmission; and
comparing the delayed transmission from the I/O circuit with the second delayed transmission to determine if the timing offset of the delayed transmission and the stored timing offset differ.
5. A system comprising:
an antenna;
a radio frequency circuit coupled to the antenna;
a controller coupled to the radio frequency circuit; and
a memory device coupled to the controller, the memory device including
a core circuit to operate in a first clock domain, and
an input/output (I/O) circuit to operate in a second clock domain different than the first clock domain, the I/O circuit to include a sequential circuit to send data to and receive data from the core circuit, and a control circuit to control operation of the sequential circuit via a timing offset signal; the core circuit to further
transmit a test data sequence to the I/O circuit,
receive a delayed transmission of the test data sequence from the sequential circuit of I/O circuit,
compare the timing offset of the delayed transmission with a stored timing offset determined during a link training between the core and I/O circuit, and
adjust the timing offset signal of the control circuit included in the I/O circuit if the timing offset of the delayed transmission and the stored timing offset differ;
wherein the first clock domain comprises at least one of a different phase or a different frequency than the second clock domain.
6. The system of claim 5 , the core circuit to transmit the test data sequence to the I/O circuit in response to the I/O circuit exiting a low power state.
7. The system of claim 5 , wherein the sequential circuit of the I/O circuit comprises a first in first out (FIFO) circuit.
8. The system of claim 5 , the core circuit to further include a delay circuit including the stored timing offset, wherein comparing the timing offset of the delayed transmission with the stored timing offset determined during the link training between the core and I/O circuit comprises:
processing the test data via the delay circuit to generate a second delayed transmission; and
comparing the delayed transmission from the I/O circuit with the second delayed transmission to determine if the timing offset of the delayed transmission and the stored timing offset differ.
9. A method comprising:
transmitting a test data sequence from a core circuit operating in a first clock domain to an I/O circuit operating in a second clock domain different than the first clock domain;
receiving a delayed transmission of the test data sequence from a sequential circuit of I/O circuit, the sequential circuit controlled via a control circuit to transmit data based on a first timing offset value;
comparing the first timing offset value of the delayed transmission with a stored timing offset determined during a link training between the core and I/O circuit; and
adjusting the first timing offset value used by the sequential circuit of the I/O circuit if the timing offset of the delayed transmission and the stored timing offset differ;
wherein the first clock domain comprises at least one of a different phase or a different frequency than the second clock domain.
10. The method of claim 9 , wherein transmitting the test data sequence from the core circuit to the I/O circuit is in response to the I/O circuit exiting a low power state.
11. The method of claim 9 , wherein the sequential circuit of the I/O circuit comprises a first in first out (FIFO) circuit.
12. The method of claim 9 , the core circuit to further include a delay circuit including the stored timing offset, the method further comprising:
processing the test data via the delay circuit to generate a second delayed transmission; and
comparing the delayed transmission from the I/O circuit with the second delayed transmission to determine if the first timing offset value and the stored timing offset differ.