IP Library Granted Patent US 8,445,303
Granted Patent B2
US 8,445,303 · App. 13/366,589 · Granted May 21, 2013

Method of manufacturing semiconductor device and semiconductor device

Inventors: Yasuto Miyake (Hirakata, JP); Ryoji Hiroyama (Kyo-tanabe, JP); Masayuki Hata (Kadoma, JP)
Assignee: Future Light, LLC
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Quick Facts
Patent No.
US 8,445,303
App. No.
13/366,589
Granted
May 21, 2013
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion.

Claims (23)

1. A method of manufacturing a semiconductor device, comprising steps of:

forming a semiconductor device layer on an upper surface of a substrate; the substrate including said upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to said upper surface and a second side closer to said lower surface;

exposing a portion of said lower surface where said dislocation concentrated region does not exist above on said lower surface by removing said substrate on said second side along with at least a part of said dislocation concentrated region; and

forming an electrode on said portion.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein

said dislocation concentrated region is so arranged as to extend substantially parallel to said upper surface, and

said step of exposing said portion includes a step of exposing said portion by removing said substrate on said second side so as to remove substantially all of said dislocation concentrated region extending substantially parallel to said upper surface.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein

said substrate includes a lower portion, said dislocation concentrated region arranged on said lower portion and an upper portion so arranged on said dislocation concentrated region that said dislocation concentrated region is not exposed on said upper surface.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein

said step of forming said semiconductor device layer on said upper surface includes a step of forming said semiconductor device layer on said portion.

5. The method of manufacturing a semiconductor device according to claim 3 , wherein

said step of exposing said portion includes a step of removing all of said lower portion, all of said dislocation concentrated region and a part of said upper portion so that said dislocation concentrated region does not exist above a substantially overall region of a portion exposed on said lower surface.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein

said step of forming said electrode includes a step of forming said electrode on said lower surface where said dislocation concentrated region does not exist.

7. The method of manufacturing a semiconductor device according to claim 1 , wherein

said dislocation concentrated region is so arranged as to obliquely extend with respect to said upper surface,

said step of exposing said portion includes a step of exposing said portion by removing said substrate on said second side so as to remove at least a part of said dislocation concentrated region.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein

said upper surface is substantially equal to a nonpolar plane.

9. The method of manufacturing a semiconductor device according to claim 1 , wherein

said step of forming said semiconductor device layer includes a step of forming a waveguide on said semiconductor device layer, and

said waveguide extends along a [1-100] direction.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2017
From: SANYO ELECTRIC CO., LTD.
To: EPISTAR CORPORATION
Reel/Frame 041652/0122 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2016
From: FUTURE LIGHT LIMITED LIABILITY COMPANY
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 040523/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2012
From: SANYO ELECTRIC CO., LTD.
To: FUTURE LIGHT, LLC
Reel/Frame 028055/0376 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2012
From: MIYAKE, YASUTO; HIROYAMA, RYOJI; HATA, MASAYUKI
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 028050/0884 →
Priority Claims (1)
JP 2007-203748 · Aug 6, 2007 · national
Continuity (3)
Division 13105386 · May 11, 2011
Division 12186168 · Aug 5, 2008
Related Publication 20120142167A1 · Jun 7, 2012