Nanostructured devices
A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.
1. A photovoltaic device comprising:
a crystalline semiconductor substrate comprising:
a bottom n-doped region;
a top p-doped region adjacent to and in direct physical contact with the n-doped region, wherein the n-doped region and the p-doped region form a p-n junction within the bulk of the crystalline semiconductor substrate, wherein the p-n junction is located at least about 30 nm from the bottom of the nanowires and the top p-doped region contains p-dopant throughout the entirety of the top p-doped region; and
a plurality of p-doped nanowires in direct physical contact with the top p-doped region of the crystalline semiconductor substrate.
2. A device as described in claim 1 , wherein the nanowires have a mean diameter sufficiently small to suppress free carrier absorption.
3. A device as described in claim 1 , wherein the nanowires are no more than about 200 nm in diameter.
4. A device as described in claim 1 , wherein the n-doped region and the p-doped region comprise silicon.
5. A device as described in claim 1 , wherein the majority of nanowires are approximately perpendicular to a crystal plane in an orientation other than <100>.
6. A device as described in claim 1 , wherein the p-n junction is located at least about 1 μm below the base of the nanowires.
7. A device as described in claim 1 , wherein the p-n junction is located at least about 0.75 μm below the base of the nanowires.
8. A device as described in claim 1 , further comprising metal particles in the vicinity of the area where the p-doped nanowires are in direct physical contact with the p-doped region.
9. A device as described in claim 1 , wherein the device is fabricated using a process comprising metal enhanced etching in a solution comprising HF and an oxidizer.
10. A device as described in claim 1 , wherein the p-n junction is located at least about 300 nm from the bottom of the nanowires.
11. A device as described in claim 1 , wherein the p-n junction is located at least about 300 nm from the bottom of all the nanowires.
12. A device as described in claim 1 , wherein the p-doped region comprises no more than about 10 18 dopants per cubic centimeter.
13. A device as described in claim 1 , wherein the crystalline semiconductor comprises polycrystalline silicon.
14. A device as described in claim 1 , wherein the p-doped nanowires are at an angle different from 90 degrees to a surface where they have direct physical contact with the p-doped region.
15. A photovoltaic device comprising:
a crystalline semiconductor substrate comprising:
a bottom p-doped region;
a top n-doped region adjacent to and in direct physical contact with the p-doped region, wherein the p-doped region and the n-doped region form a p-n junction within the bulk of the crystalline semiconductor substrate, wherein the p-n junction is located at least about 30 nm from the bottom of the nanowires and the top n-doped region contains n-dopant throughout the entirety of the top n-doped region; and
a plurality of n-doped nanowires in direct physical contact with the top n-doped region of the crystalline semiconductor substrate.
16. A device as described in claim 15 , wherein the nanowires have a mean diameter sufficiently small to suppress free carrier absorption.
17. A device as described in claim 15 , wherein the nanowires are no more than about 200 nm in diameter.
18. A device as described in claim 15 , wherein the n-doped region and the p-doped region comprise silicon.
19. A device as described in claim 15 , wherein the majority of nanowires are approximately perpendicular to a crystal plane in an orientation other than <100>.
20. A device as described in claim 15 , wherein the p-n junction is located at least about 1 μm below the base of the nanowires.
21. A device as described in claim 15 , wherein the p-n junction is located at least about 0.75 μm below the base of the nanowires.
22. A device as described in claim 15 , further comprising metal particles in the vicinity of the area where the n-doped nanowires are in direct physical contact with the n-doped region.
23. A device as described in claim 15 , wherein the device is fabricated using a process comprising metal enhanced etching in a solution comprising HF and an oxidizer.
24. A device as described in claim 15 , wherein the p-n junction is located at least about 300 nm from the bottom of the nanowires.
25. A device as described in claim 15 , wherein the p-n junction is located at least about 300 nm from the bottom of all the nanowires.
26. A device as described in claim 15 , wherein the n-doped region comprises no more than about 10 18 dopants per cubic centimeter.
27. A device as described in claim 15 , wherein the crystalline semiconductor comprises polycrystalline silicon.
28. A device as described in claim 15 , wherein the p-doped nanowires are at an angle different from 90 degrees to a surface where they have direct physical contact with the p-doped region.