IP Library Granted Patent US 8,450,776
Granted Patent B2
US 8,450,776 · App. 13/528,574 · Granted May 28, 2013

Epitaxial devices

Inventors: Anton deVilliers (Boise, ID); Erik Byers (Boise, ID); Scott Sills (Boise, ID)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,450,776
App. No.
13/528,574
Granted
May 28, 2013
Kind
B2
Abstract

Epitaxial devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Claims (31)

1. A semiconductor device, comprising:

a substrate;

an epitaxial material formed over a substrate, the epitaxial material having a lattice constant that is different from the substrate;

a textured surface formed on the substrate, wherein a geometry of the textured surface reduces a concentration of crystallographic defects associated with a lattice mismatch between the epitaxial material and the substrate.

2. The semiconductor device of claim 1 , wherein the substrate includes a silicon substrate.

3. The semiconductor device of claim 1 , wherein the epitaxial material includes gallium nitride.

4. The semiconductor device of claim 1 , wherein the textured surface comprises an array of island texture features.

5. The semiconductor of claim 4 , wherein the island texture features comprise a number of pyramid shaped structures.

6. The semiconductor device of claim 4 , wherein the island texture features comprise a number of conical-shaped structures.

7. The semiconductor device of claim 1 , wherein the textured surface comprises an array of linear texture features.

8. A semiconductor device, comprising:

a textured substrate, wherein the texture includes a number of periodically repeating angled surfaces with a surface normal vector that is between 0 degrees and 90 degrees with respect to a plane of the surface of the substrate; and

a liquid crystal medium in contact with the textured substrate.

9. The semiconductor device of claim 8 , wherein the textured substrate comprises a silicon substrate.

10. The semiconductor device of claim 8 , wherein the textured substrate comprises an indium tin oxide substrate.

11. The semiconductor device of claim 8 , wherein the textured substrate comprises a number of pyramid shaped structures.

12. The semiconductor device of claim 8 , wherein the textured substrate comprises a number of linear structures.

13. The semiconductor device of claim 8 , wherein the textured substrate comprises a number of conical-shaped structures.

14. A semiconductor device, comprising:

a substrate;

an epitaxial gallium nitride material formed over the substrate;

a textured surface formed on the substrate, wherein a geometry of the textured surface reduces a concentration of crystallographic defects associated with a lattice mismatch between the gallium nitride material and the substrate; and

one or more semiconductor layers formed on the epitaxial gallium nitride layer to form a P-N junction.

15. The semiconductor device of claim 14 , wherein the semiconductor device is a light emitting diode.

16. The semiconductor device of claim 14 , wherein the substrate includes a silicon substrate.

17. The semiconductor device of claim 14 , wherein the textured surface comprises an array of island texture features.

18. The semiconductor of claim 17 , wherein the island texture features comprise a number of pyramid shaped structures.

19. The semiconductor device of claim 17 , wherein the island texture features comprise a number of conical-shaped structures.

20. The semiconductor device of claim 14 , wherein the textured surface comprises an array of linear texture features.

21. The semiconductor device of claim 14 , wherein the textured surface comprises an array of texture features having angled faces with surface normal vector between 0 degrees and 90 degrees with respect to a surface plane of the substrate.

22. The semiconductor device of claim 21 , wherein the angled faces are positioned between approximately 10 and 15 degrees with respect to the surface plane of the substrate.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2014
From: DEVILLIERS, ANTON; BYERS, ERIK; SILLS, SCOTT E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032790/0440 →
Continuity (2)
Division 12826275 · Jun 29, 2010
Related Publication 20120256191A1 · Oct 11, 2012