Semiconductor device and production method thereof
An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.
1. A semiconductor device comprising:
a first memory cell and a second memory cell formed over a main face of a semiconductor substrate,
wherein the first memory cell includes:
a first well of a first conductivity type formed in the semiconductor substrate;
a first gate insulation film formed over the first well;
a first control gate electrode formed over the semiconductor substrate through the first gate insulation film and having a first side face and a second side face positioned at opposite sides of the first control gate electrode;
a second gate insulation film extendedly formed over the first side face of the first control gate electrode and the first well and containing a first charge retention film;
a first memory gate electrode formed over the first side face of the first control gate electrode and insulated from the first control gate electrode and the semiconductor substrate through the second gate insulation film;
a first drain region comprised of a semiconductor region of a second conductivity type opposite the first conductivity type, and formed over the semiconductor substrate in the vicinity of the first control gate electrode; and
a first source region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the first memory gate electrode,
wherein the second memory cell includes:
a second well of the first conductivity type formed in the semiconductor substrate;
a third gate insulation film formed over the second well;
a second control gate electrode formed over the semiconductor substrate through the third gate insulation film and having a third side face and a fourth side face positioned at opposite sides of the second control gate electrode;
a fourth gate insulation film extendedly formed over the third side face of the second control gate electrode and the second well and containing a second charge retention film;
a second memory gate electrode formed over the third side face of the second control gate electrode and insulated from the second control gate electrode and the semiconductor substrate through the fourth gate insulating film;
a second drain region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the second control gate electrode; and
a second source region comprised of a semiconductor region of the second conductivity type formed over the semiconductor substrate in the vicinity of the second memory gate electrode,
wherein a first gate length of the first memory gate electrode of the first memory cell is longer than a second gate length of the second memory gate electrode of the second memory cell.
2. A semiconductor device according to claim 1 , wherein a first height of a top face of the first memory gate electrode of the first memory cell is lower than a second height of a top face of the first control gate electrode of the first memory cell, and
wherein a third height of a top face of the second memory gate electrode of the second memory cell is lower than a fourth height of a top face of the second control gate electrode of the second memory cell.
3. A semiconductor device according to claim 1 , wherein the first memory cell is used for storing data and the second memory cell is used for programs.
4. A semiconductor device according to claim 1 , wherein the second memory gate electrode in the second memory cell is formed in the shape of a sidewall.
5. A semiconductor device according to claim 1 , wherein the first memory gate electrode in the first memory cell is formed so as to cover the first side face and a top face of the first control gate electrode in the first memory cell through the second gate insulation film and overhang the top face of the first control gate electrode in the first memory cell.
6. A semiconductor device according to claim 1 , the first charge retention film and the second charge retention film each contain a silicon nitride film.
7. A semiconductor device according to claim 1 ,
wherein the first memory cell further includes a fifth gate insulation film and a third memory gate electrode,
wherein the fifth gate insulation film is formed over the second side face of the first control gate electrode and the first well and contains a third charge retention film,
wherein the third memory gate electrode is formed over the second side face of the first control gate electrode and is insulated from the first control gate electrode and the semiconductor substrate through the fifth gate insulation film, and
wherein a third gate length of the third memory gate electrode is the same as the first gate length of the first memory gate electrode.
8. A semiconductor device according to claim 1 ,
wherein the second memory cell further includes a sixth gate insulation film and a fourth memory gate electrode,
wherein the sixth gate insulation film is formed over the fourth side face of the second control gate electrode and the second well and contains a fourth charge retention film,
wherein the fourth memory gate electrode is formed over the fourth side face of the second control gate electrode and is insulated from the second control gate electrode and the semiconductor substrate through the sixth gate insulation film, and
wherein a fourth gate length of the fourth memory gate electrode is the same as the second gate length of the second memory gate electrode.
9. A semiconductor device according to claim 1 ,
wherein the first charge retention film has a first portion overlapping the first memory gate electrode,
wherein the second charge retention film has a second portion overlapping the second memory gate electrode,
wherein a first overlap length is a length of the first portion in a direction in which the first control gate electrode and first memory gate electrode adjoin,
wherein a second overlap length is a length of the second portion in a direction in which the second control gate electrode and second memory gate electrode adjoin, and
wherein the first overlap length is longer than the second overlap length.