Wiring substrate
A wiring substrate includes plural wiring layers and plural insulation layers being alternately stacked one on top of the other. The plural insulation layers are formed with insulation resin having the same composition. The plural insulation layers are formed with a filler having the same composition. The filler content of each of the plural insulation layers ranges from 30 vol % or more to 65 vol % or less. The thermal expansion coefficient of each of the plural insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.
1. A wiring substrate comprising:
a plurality of wiring layers and a plurality of insulation layers being alternately stacked one on top of the other;
a first main surface; and
a second main surface that is positioned on a side opposite of the first main surface;
wherein the plurality of insulation layers include
an insulation layer being positioned nearest to the second main surface among the plurality of insulation layers, the insulation layer including a plurality of opening parts and a reinforcement member,
wherein the plurality of wiring layers include
a plurality of first electrode pads that are exposed toward the first main surface,
a plurality of second electrode pads that are formed in the plurality of opening parts and exposed toward the second main surface,
wherein a pitch between the plural second electrode pads is greater than a pitch between the plural first electrode pads,
wherein the plurality of insulation layers are formed with an insulation resin having the same composition,
wherein the plurality of insulation layers are formed with a filler having the same composition,
wherein the filler content of each of the plurality of insulation layers ranges from 30 vol % or more to 65 vol % or less, and
wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.
2. The wiring substrate as claimed in claim 1 , wherein the filler content of each of the plurality of insulation layers ranges from 55 vol % or more to 65 vol % or less, wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 17 ppm/° C. or less.
3. The wiring substrate as claimed in claim 1 , wherein the reinforcement member includes fiber bundles that are woven into a lattice-like configuration.
4. The wiring substrate as claimed in claim 1 , wherein a sidewall of each of the plurality of opening parts includes a cross section having a concave round shape, wherein the plurality of opening parts include a concave part formed in the plurality of second electrode pads exposed at bottom parts of the plurality of opening parts.
5. The wiring substrate as claimed in claim 4 , wherein a sidewall of the concave part has an outermost edge part that matches an innermost edge part of the sidewall of each of the plurality of opening parts.
6. The wiring substrate as claimed in claim 4 , wherein the sidewall of each of the plurality of opening parts has a surface roughness that is greater than a surface roughness of an upper surface of the insulation layer.
7. A semiconductor package comprising:
a wiring substrate; and
a semiconductor chip mounted on the wiring substrate via a plurality of bumps;
wherein the wiring substrate includes
a plurality of wiring layers and a plurality of insulation layers being alternately stacked one on top of the other;
a first main surface; and
a second main surface that is positioned on a side opposite of the first main surface;
wherein the plurality of insulation layers include
an insulation layer being positioned nearest to the second main surface among the plurality of insulation layers, the insulation layer including a plurality of opening parts and a reinforcement member,
wherein the plurality of wiring layers include
a plurality of first electrode pads that are exposed toward the first main surface,
a plurality of second electrode pads that are formed in the plurality of opening parts and exposed toward the second main surface,
wherein a pitch between the plural second electrode pads is greater than a pitch between the plural first electrode pads,
wherein the plurality of insulation layers are formed with an insulation resin having the same composition,
wherein the plurality of insulation layers are formed with a filler having the same composition,
wherein the filler content of each of the plurality of insulation layers ranges from 30 vol % or more to 65 vol % or less, and
wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.
8. A wiring substrate comprising:
a plurality of wiring layers and a plurality of insulation layers being alternately stacked one on top of the other;
a first main surface; and
a second main surface that is positioned on a side opposite of the first main surface;
wherein the plurality of insulation layers include
one insulation layer being positioned nearest to the second main surface among the plurality of insulation layers and including a plurality of opening parts,
another insulation layer being positioned nearer to the first main surface than the one insulation layer and including a reinforcement member;
wherein the plurality of wiring layers include
a plurality of first electrode pads that are exposed toward the first main surface, and
a plurality of second electrode pads that are formed in the plurality of opening parts and exposed toward the second main surface;
wherein a pitch between the plurality of second electrode pads is greater than a pitch between the plurality of first electrode pads,
wherein the plurality of insulation layers are formed with an insulation resin having the same composition,
wherein the plurality of insulation layers are formed with a filler having the same composition,
wherein the filler content of each of the plurality of insulation layers ranges from 30 vol % or more to 65 vol % or less, and
wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.
9. The wiring substrate as claimed in claim 8 , wherein the filler content of each of the plurality of insulation layers ranges from 55 vol % or more to 65 vol % or less, wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 17 ppm/° C. or less.
10. The wiring substrate as claimed in claim 8 , wherein the reinforcement member includes fiber bundles that are woven into a lattice-like configuration.
11. The wiring substrate as claimed in claim 8 , wherein a sidewall of each of the plurality of opening parts includes a cross section having a concave round shape, wherein the plurality of opening parts include a concave part formed in the plurality of second electrode pads exposed at bottom parts of the plurality of opening parts.
12. The wiring substrate as claimed in claim 11 , wherein a sidewall of the concave part has an outermost edge part that matches an innermost edge part of the sidewall of each of the plurality of opening parts.
13. The wiring substrate as claimed in claim 11 , wherein the sidewall of each of the plurality of opening parts has a surface roughness that is greater than a surface roughness of an upper surface of the one insulation layer.
14. A semiconductor package comprising:
a wiring substrate; and
a semiconductor chip mounted on the wiring substrate via a plurality of bumps;
wherein the wiring substrate includes
a plurality of wiring layers and a plurality of insulation layers being alternately stacked one on top of the other;
a first main surface; and
a second main surface that is positioned on a side opposite of the first main surface;
wherein the plurality of insulation layers include
one insulation layer being positioned nearest to the second main surface among the plurality of insulation layers and including a plurality of opening parts,
another insulation layer being positioned nearer to the first main surface than the one insulation layer and including a reinforcement member;
wherein the plurality of wiring layers include
a plurality of first electrode pads that are exposed toward the first main surface, and
a plurality of second electrode pads that are formed in the plurality of opening parts and exposed toward the second main surface;
wherein a pitch between the plurality of second electrode pads is greater than a pitch between the plurality of first electrode pads,
wherein the plurality of insulation layers are formed with an insulation resin having the same composition,
wherein the plurality of insulation layers are formed with a filler having the same composition,
wherein the filler content of each of the plurality of insulation layers ranges from 30 vol % or more to 65 vol % or less, and
wherein the thermal expansion coefficient of each of the plurality of insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.