IP Library › Granted Patent US 8,455,984
Granted Patent B2
US 8,455,984 · App. 12/946,445 · Granted Jun 4, 2013

Integrated circuit structure and method of forming the same

Inventors: Kee Wei Chung (Taipei County, TW); Chiang Hung Lin (Taipei County, TW); Neng Tai Shih (Taoyuan County, TW)
Assignee: Nanya Technology Corp.
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Quick Facts
Patent No.
US 8,455,984
App. No.
12/946,445
Granted
Jun 4, 2013
Kind
B2
Abstract

A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole.

Claims (12)

1. An integrated circuit structure, comprising:

a semiconductor substrate having a first side and a second side opposite the first side;

a conductive via extending from the first side of the semiconductor substrate, wherein the bottom of the conductive via protrude from the second side of the semiconductor substrate;

a diffusion barrier layer positioned along a sidewall and a bottom surface of the conductive via;

a first dielectric layer positioned along the diffusion barrier layer;

a photosensitive dielectric layer formed on the second side of the semiconductor substrate, wherein the photosensitive dielectric layer has an opening; and

a solder bump positioned in the opening and electrically connected to the conductive via,

wherein the diffusion barrier layer is disposed between the conductive via and the solder bump, and

wherein the conductive via, the diffusion barrier layer, and the first dielectric layer are positioned in this order.

2. The integrated circuit structure of claim 1 , further comprising a second dielectric layer between the semiconductor substrate and the photosensitive dielectric layer.

3. The integrated circuit structure of claim 2 , wherein the second dielectric layer is a silicon nitride layer.

4. The integrated circuit structure of claim 1 , wherein the photosensitive dielectric layer is made of a material selected from the group consisting of polybenzoxazoles (PBO), polybenzimidazoles, polyimides (PI), phenolic resins and a combination thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2010
From: CHUNG, KEE WEI; LIN, CHIANG HUNG; SHIH, NENG TAI
To: NANYA TECHNOLOGY CORP.
Reel/Frame 025304/0691 →
Continuity (1)
Related Publication 20120119355A1 · May 17, 2012