DRAM device with built-in self-test circuitry

1. A dynamic random access memory (DRAM) device comprising:

a first integrated circuit (IC) die having test circuitry to generate redundancy information;

a second IC die coupled to the first IC die in a packaged configuration and having primary storage cells and redundant storage cells, the second IC die including redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

2. The DRAM device of claim 1 wherein the redundancy information is determined during a test sequence performed between the first IC die and the second IC die.

3. The DRAM device of claim 1 wherein the first IC die includes storage circuitry to retain the redundancy information.

4. The DRAM device of claim 3 wherein the storage circuitry comprises non-volatile memory.

5. The DRAM device of claim 1 and further including a third IC die comprising non-volatile storage circuitry to retain the redundancy information.

6. The DRAM device of claim 1 wherein the packaged configuration comprises the first and second IC dies being disposed within the same IC package.

7. The DRAM device of claim 1 wherein the packaged configuration comprises the first and second IC dies disposed in a stacked orientation.

8. The DRAM device of claim 1 wherein the first and second IC dies are coupled via a serial port interface, and the redundancy information is communicated between the dies via the serial port interface.

9. The DRAM device of claim 1 wherein the second IC die includes a programmable register to load the redundancy information upon an initialization sequence.

10. The DRAM device of claim 9 wherein the redundancy circuitry includes selection circuitry to receive values stored in the programmable register, the selection circuitry to select redundant storage cells based on the values as substitute storage locations for defective primary storage cells.

11. The DRAM device of claim 1 wherein the test circuitry includes:

pattern generation circuitry to transmit test signal sequences;

comparison circuitry to receive signals from the second IC die responsive to the test signal sequences; and

failure analysis circuitry to identify defective primary storage locations.

12. The DRAM device of claim 1 wherein the first IC die comprises a logic IC die manufactured in accordance with a logic-optimized manufacturing process.

13. The DRAM device of claim 1 wherein the second IC die comprises a memory IC die manufactured in accordance with a memory-optimized manufacturing process.

14. A DRAM memory module comprising:

a substrate formed with signal traces; and

a plurality of DRAM devices mounted on the substrate and coupled to the signal traces, each of the DRAM devices including:

a first integrated circuit (IC) die having test circuitry to generate redundancy information, and

a second IC die coupled to the first IC die in a packaged configuration and having primary rows and columns of storage cells and redundant rows and columns of storage cells, the second IC die including redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more of the redundant storage cells.

15. The DRAM module according to claim 14 and further including:

a third IC die mounted on the substrate, the third IC die comprising non-volatile storage circuitry to retain the redundancy information.

16. The DRAM module according to claim 14 wherein the redundancy information is determined during a test sequence performed between each first IC die and each second IC die of the plurality of DRAM devices.

17. The DRAM module according to claim 16 wherein the test circuitry for each of the DRAM devices carries out the test sequence with the devices mounted on the module.

18. A method of operation in a memory circuit having a logic IC die packaged with at least one memory IC die, the memory IC die having primary storage cells and redundant storage cells, the method comprising:

performing a test sequence between the logic IC die and the memory IC die to determine one or more groups of defective primary storage cells;

generating redundancy information representing a mapping of the defective primary storage cells to a portion of the redundant storage cells; and

storing the redundancy information.

19. The method of claim 18 and further comprising:

accessing the stored redundancy information; and

substituting the defective primary storage cells for a portion of the redundant storage cells based on the stored redundancy information.

20. The method of claim 19 wherein:

performing a test sequence and generating redundancy information are carried out in an initialization mode; and

accessing and substituting are carried out in a normal operation mode.

21. The method of claim 18 wherein performing a test sequence comprises:

generating a pattern of test signals from the logic IC die to the memory IC die;

receiving data signals from the memory IC die responsive to the test signals; and

comparing the received data signals from the memory IC die to expected data signals.

22. The method of claim 18 wherein generating redundancy information comprises:

analyzing failures identified from the comparing to identify the defective primary storage cells.

23. A DRAM device comprising:

a logic IC die;

a memory IC die coupled to the logic IC die, the memory IC die having primary storage cells and redundant storage cells;

the logic IC die including

means for performing a test sequence between the logic IC die and the memory IC die to determine one or more groups of defective primary storage cells;

means for generating redundancy information representing a mapping of the defective primary storage cells to a portion of the redundant storage cells; and

means for storing the redundancy information.

24. The DRAM device according to claim 23 wherein the memory IC die further comprises:

means for accessing the stored redundancy information; and

means for substituting the defective primary storage cells with a portion of the redundant storage cells based on the stored redundancy information.