High speed syndrome-based FEC encoder and system using same
A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.
1. A communication system, comprising:
a decoder system comprising:
a plurality of N-parallel syndrome generators, each of the N-parallel syndrome generators coupled to a parallel input data stream and being adapted to perform a calculation each cycle with N symbols from the input parallel data stream;
a plurality of key equation determination devices, each key equation determination device coupled to at least one of the N-parallel syndrome generators and being adapted to determine at least one error polynomial;
a plurality of N-parallel error determination and correcting devices, one for each of the N-parallel syndrome generators, each N-parallel error correction and determination device coupled to one of the key equation determination devices and being adapted to use the at least one error polynomial produced by the one key equation determination device to correct errors in the parallel input data stream; and
an encoder system coupled to the decoder system and comprising:
a plurality of N-parallel encoders, each of the N-parallel encoders adapted to accept N symbol inputs, in parallel, during a cycle and produce, in parallel, N symbol outputs during a cycle, and wherein each N-parallel encoder is adapted to produce a plurality of redundancy symbols after a predetermined number of input symbols have been input to the encoder, wherein said N symbol inputs comprise a plurality of input bits, wherein said plurality of redundancy symbols comprise a plurality of output bits, wherein each N-parallel encoder comprises an input delay unit and an output delay unit, wherein each input delay unit delays only a subset of said plurality of input bits, and wherein each output delay unit delays only a subset of said plurality of output bits; and
a device coupled to the N-parallel encoders and adapted to create an M-parallel frame, the M-parallel frame adapted to hold a plurality of codewords, each codeword comprising a plurality of symbols.
2. The communication system of claim 1 , wherein N is three, wherein the encoder is adapted to encode 40 gigabits per second (Gb/s), and wherein the decoder is adapted to decode 40 Gb/s.
3. The communication system of claim 1 , wherein the system is part of a Synchronous Optical Network (SONET), wherein the decoder of the system is coupled to an optical receiver and the encoder is coupled to an optical transmitter, the optical receiver converting an optical data stream into a serial input data stream, the decoder further comprising a device adapted to convert the serial input data stream into the parallel input data stream, the encoder further comprising a device adapted to convert symbols from the N-parallel data stream to a serial output data stream that is coupled to the optical transmitter.
4. The communication system of claim 1 , further comprising a second device coupled to the M-parallel frame and adapted to create a serial data stream from a plurality of symbols in the M-parallel frame.
5. The communication system of claim 1 , wherein said encoder further comprises a third device adapted to create frame alignment information, the frame alignment information passed through one of the N-parallel encoders and placed at a beginning of the M-parallel frame.
6. The communication system of claim 1 , wherein said encoder further comprises a third device coupled to the second device and being adapted to create a parallel data stream having a width of 48 symbols, wherein the encoder outputs 48 symbols per clock cycle and wherein N=3 and M=16.